Stacked Memory Package Layout for Shorter SoC Routing
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Solution Overview
Problem
Current electronic packaging architectures require a large form factor and significant routing lengths, leading to signal integrity issues and limitations in die size reduction due to memory modules being placed adjacent to the SoC die, which also necessitate complex redesigns and increased costs.
Innovation Solution
Implementing a memory package architecture where the memory die module is positioned above the SoC die with memory routing integrated into an underlying base die or mold layer, reducing the layer count of the package substrate and allowing for smaller form factors without the need for through-silicon vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory modules are placed side-by-side with the CPU die, then routing can be provided through the package substrate, but the package XY area increases significantly and routing layers increase to at least five layers
Solution Approach 1:
The patent transitions from a two-dimensional side-by-side layout to a three-dimensional stacked architecture, placing the memory die module vertically above the SoC die. This dimensional change allows memory and compute functions to coexist in the same package footprint without increasing XY area, while routing is provided through the base die substrate rather than requiring multiple package substrate layers
2Reliability
If memory modules are placed side-by-side with the CPU die, then routing can be provided through the package substrate, but the routing length increases to 20 mm or longer
Solution Approach 1:
By stacking the memory die module vertically above the SoC die, the patent dramatically reduces the horizontal distance between memory and compute components. This vertical integration reduces routing length from 20 mm or longer to significantly shorter paths through the base die, improving signal integrity and enabling higher-speed memory interfaces
3Volume of moving object
If memory chiplets are stacked on the SoC die using through silicon vias, then vertical integration is achieved, but the assembly flow becomes more complex and requires redesign of the memory die module
Solution Approach 1:
The patent introduces a base die substrate as an intermediary layer between the SoC die and the memory die module. This base die provides the routing infrastructure and mechanical support, allowing the memory die module to be wire-bonded to the base die without requiring through-silicon-vias through the SoC die itself. This mediator approach simplifies the assembly flow by decoupling the memory stacking requirement from the SoC die structure
Solution Approach 2:
The patent segments the package into distinct functional layers: the SoC die for compute functions, the base die substrate for routing and support, and the memory die module for memory functions. This segmentation allows each component to be optimized and manufactured independently, with the base die serving as an intermediate platform that simplifies the integration of the memory stack without requiring complex through-silicon-via processes
4Reliability
If DDR physical layer occupies a long die shoreline, then memory interface is provided, but die size reduction is limited
Solution Approach 1:
By moving the memory die module to a vertical stack above the SoC die, the patent reduces the horizontal shoreline requirement on the SoC die. The memory interface can be provided through a smaller footprint on the SoC die edge, while the full memory capacity is achieved through the stacked memory dies above, enabling greater die size reduction for the SoC
Data Source
AI summary
Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, and a base coupled to the package substrate. In an embodiment, a die is coupled to the base, and a memory die module is over the die. In an embodiment, the memory die module is communicatively coupled to the die through routing provided on the base