Stacked Semiconductor Memory Source-Line Isolation Between Planes
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor memory technologies face challenges in maintaining data reliability due to increased noise components in source lines, particularly when adjacent planes share structural bodies without adequate electrical insulation.
Innovation Solution
The semiconductor memory design incorporates a source line separation region between planes, ensuring electrical insulation of conductors between planes and reducing noise components, thereby enhancing data reliability and minimizing chip area by optimizing the lead region layout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If adjacent planes share structural bodies to minimize chip area, then chip area is reduced, but noise components in source lines increase and data reliability deteriorates
Solution Approach 1:
The source line separation region divides the continuous source line into electrically isolated segments between adjacent planes. This segmentation prevents noise propagation while maintaining the compact stacked structure, resolving the contradiction between chip area minimization and data reliability.
Solution Approach 2:
The source line separation region acts as an intermediary insulating structure between the source lines of adjacent planes. This mediator provides electrical insulation that blocks noise components while allowing the planes to share structural bodies, thus maintaining small chip area while improving data reliability.
2Device complexity
If planes share structural bodies without separation, then manufacturing complexity is reduced, but noise components increase and reliability deteriorates
Solution Approach 1:
The source line separation region segments the source line structure into isolated regions for each plane. This segmentation adds minimal structural complexity while effectively preventing noise coupling, thus improving reliability without significantly increasing device complexity.
Solution Approach 2:
The source line separation region applies electrical insulation locally at critical interfaces between planes, rather than throughout the entire structure. This localized approach maintains overall structural simplicity while providing noise isolation where most needed, resolving the contradiction between complexity and reliability.
3Reliability
If source lines are electrically insulated between planes, then noise components are reduced and reliability improves, but chip area increases
Solution Approach 1:
The source line separation region is nested within the existing stacked structure of adjacent planes, utilizing the vertical space between planes rather than expanding the horizontal chip area. This nesting approach provides electrical insulation while maintaining compact chip footprint.
Solution Approach 2:
The source line separation region utilizes the vertical dimension between stacked planes to provide electrical insulation, rather than requiring additional horizontal space. This dimensional approach allows noise isolation without increasing chip area, resolving the contradiction between reliability improvement and area minimization.
Data Source
AI summary
A semiconductor memory includes first to fourth stacked bodies. The first stacked body includes a first conductor, and an alternating stack of first insulators and second conductors above the first conductor in a region. The second stacked body includes a third conductor, and an alternating stack of second insulators and fourth conductors above the third conductor in another region. The third stacked body includes a fifth conductor adjacent to the first conductor via a third insulator in a separation region. The fourth stacked body includes a seventh conductor adjacent to the third conductor via a fifth insulator in the separation region. The fifth conductor is electrically insulated from the seventh conductor.