3D Stacked Memory Cell Source-Line Contact Layout for Higher Yield
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor memory devices face challenges in improving yield and reducing manufacturing costs due to complex interconnect structures and variations in contact hole formation during the manufacturing process of three-dimensionally stacked memory cells.
Innovation Solution
The semiconductor memory device employs a configuration with memory pillars and support pillars that pass through stacked interconnects, allowing for electrical coupling of the source line to the interconnect below the memory cell array, using shared processes for pillar formation and reducing the complexity of contact hole formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If complex interconnect structures are used for three-dimensionally stacked memory cells, then device functionality is improved, but manufacturing yield deteriorates and costs increase
Solution Approach 1:
The patent merges the formation of memory pillars and support pillars into a single shared manufacturing process. Both types of pillars are formed simultaneously using the same etching and filling operations, reducing process complexity and improving yield while maintaining the three-dimensional stacked memory cell functionality
Solution Approach 2:
The support pillars serve multiple functions: they provide structural support for the stacked memory cells and simultaneously act as contact holes for electrical coupling. This multi-functionality reduces the number of separate manufacturing steps needed, thereby improving yield and reducing costs
2Adaptability or versatility
If complex interconnect structures are used for three-dimensionally stacked memory cells, then device functionality is improved, but manufacturing costs increase
Solution Approach 1:
The patent combines multiple manufacturing operations into shared processes. The same etching and filling steps are used to form both memory pillars and support pillars, reducing the total number of manufacturing steps and associated costs while maintaining full device functionality
3Ease of manufacture
If variations in contact hole formation occur during manufacturing, then manufacturing complexity increases, but yield deteriorates
Solution Approach 1:
The patent eliminates separate contact hole formation steps by integrating the support pillar formation with the memory pillar formation process. This merging removes a source of manufacturing variations and improves yield while maintaining the necessary electrical coupling functionality
Solution Approach 2:
The support pillars act as intermediary structures that simultaneously provide structural support and serve as contact holes for electrical coupling. This intermediary function eliminates the need for separate contact hole formation steps, reducing manufacturing complexity and variations
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes first and second conductor layers, a first pillar, a first contact, and a source line drive circuit. The first pillar is passing through the second conductor layers. The first pillar includes a first semiconductor layer and a second insulator layer. The first semiconductor layer includes a side surface partially in contact with the first conductor layer. The first contact is passing through the second conductor layers. The first contact includes a third conductor layer and a third insulator layer. The third conductor layer includes a side surface partially in contact with the first conductor layer. The source line drive circuit is electrically coupled to the first conductor layer via the first contact.