Stacked Memory Spare-Block Control for Yield and Access Timing
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Solution Overview
Problem
Existing stacked semiconductor modules face challenges with increased yield loss due to the number of signal lines from an interface die, lack of control over I/O operation timing, and inefficiencies in managing defective memory cells.
Innovation Solution
A stacked memory system with multiple memory chips, each equipped with a regular and spare memory block, an address storage unit, comparison unit, specifying unit, timing control unit, and execution unit, allowing for independent access timing control and substitution of defective cells, and a method involving wafer stacking, substitution, and dicing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Extent of automation
If one interface die controls all dies in the stacked module, then centralized control is achieved, but the number of signal lines (TSVs or micro bumps) increases and yield decreases
Solution Approach 1:
The patent divides the control function into two parts: the interface die performs substitution control (comparing addresses and determining substitution needs), while each memory die performs timing control (controlling its own I/O operations). This segmentation reduces signal lines between the interface die and memory dies, improving yield while maintaining automated control.
2Reliability
If each die has a comparison circuit for defect substitution, then substitution capability is improved, but information about which die accesses the interface die is not provided and timing control is lost
Solution Approach 1:
The patent separates substitution control functions (located in the interface die) from timing control functions (located in each memory die). Each memory die independently determines its own access timing based on substitution results, eliminating the need for complex centralized timing coordination while maintaining substitution capability.
Solution Approach 2:
Each memory die autonomously controls its own I/O operation timing based on substitution information received from the interface die. This self-service approach eliminates the need for the interface die to provide detailed timing control information to each memory die, simplifying the overall system while maintaining functionality.
3Reliability
If spare memory blocks are used to substitute defective cells, then yield is improved, but access timing coordination between multiple memory chips becomes complex
Solution Approach 1:
The patent divides timing control into two levels: the interface die handles substitution determination (which spare block to use), and each memory die independently handles timing control for its own I/O operations. This segmentation simplifies coordination by allowing each memory die to autonomously manage its timing based on substitution results, rather than requiring complex centralized timing coordination.
Solution Approach 2:
Each memory die autonomously determines and controls its own access timing based on substitution information from the interface die. This self-service mechanism eliminates the need for complex timing coordination protocols between the interface die and multiple memory chips, reducing system complexity while maintaining yield improvements through spare block substitution.
Data Source
AI summary
Provided is a stacked memory with an improved yield rate and with which suitable operation timing control is possible. Also provided is a manufacturing method therefor. Provided is a stacked memory 1 obtained by stacking a plurality of memory chips, wherein the memory chips each include a plurality of memory cells, and comprise: a memory unit 20 that is capable of storing data and has a normal memory block 21 used mainly for reading and writing data and a spare memory block 22 substituted for a defective memory cell in the normal memory block 21; an address storage unit 30 that, for each of two or more stacked memory chips, stores a slice address identifying a memory chip serving as an object to undergo substitution of the normal memory block 21 with the spare memory block 22 as a substitution source slice address, and stores a memory address serving as the object to undergo substitution as a substitution source memory address; a comparison unit 50 that compares a request address indicating the slice address and memory address of an access request destination, and the substitution source address; a specification unit 60 that, on the basis of the comparison results, specifies the memory unit 20 that is actually to be accessed and generates an access timing; a timing control unit 80 that selects one from among the generated access timing and access timings transmitted from the other memory chips, and controls access to the memory unit 20 at the selected access timing; and an execution unit 70 that executes reading and writing to the specified memory unit 20 at the selected access timing.