Stacked Memory Row-Hammer Mitigation With Spare Counters
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Solution Overview
Problem
Memory systems with stacked semiconductor dies are vulnerable to row hammer attacks, where repeated access to a row of memory cells can corrupt neighboring rows, and existing counter-based mitigation techniques suffer from errors that reduce reliability and performance.
Innovation Solution
Implementing spare counters at the logic die to track access operations and evaluate refresh signaling, compensating for errors in array die counters to enhance row hammer mitigation reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If counter-based mitigation techniques are used to detect row hammer attacks, then row hammer detection capability is improved, but reliability deteriorates due to counter errors
Solution Approach 1:
A logic die is introduced as an intermediary between the array die and the host system. The logic die receives access operations, generates refresh signaling based on counter values, and sends commands to the array die. This intermediary architecture allows the system to use less reliable counters on the array die while maintaining overall reliability through error tolerance in the logic die's refresh signaling generation.
Solution Approach 2:
The system implements feedback by continuously monitoring counter values and dynamically generating refresh signaling when thresholds are exceeded. The logic die monitors the counter values from the array die and adjusts refresh operations accordingly, creating a closed-loop feedback mechanism that mitigates row hammer attacks while adapting to counter reliability variations.
2Reliability
If refresh operations are performed frequently to mitigate row hammer attacks, then data integrity is improved, but system performance deteriorates due to unnecessary refresh overhead
Solution Approach 1:
The system performs refresh operations selectively rather than continuously. Refresh signaling is generated only when counter values exceed predetermined thresholds, implementing partial action. This approach applies refresh operations only when potentially needed (when row hammer attacks are detected) rather than excessively refreshing all rows continuously, thereby maintaining data integrity while reducing unnecessary performance overhead.
Data Source
AI summary
Methods, systems, and devices for row hammer mitigation reliability in stacked memory architectures are described. A spare counter may be implemented at a first interface block of a logic die to enable increased reliability and efficiency in row hammer mitigation. The first interface block may use a spare counter in case of an error associated with a counter at a memory array die. A second interface block of an array die may identify an error associated with a counter of a memory array and may transmit an indication of the error to the first interface block. The first interface block may receive the indication and may activate a spare counter to track access operations on (e.g., activations of) the row based on the indication. The first interface block may use the spare counter to evaluate whether to transmit refresh signaling to the second interface block for row hammer mitigation.