Stacked Memory Timing Alignment with SPID-Based Latency Control
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Solution Overview
Problem
Conventional multichip arrangements, such as SIMM and DIMM configurations, are not suitable for large I/O and density structures, and vertical stacking using through-silicon vias (TSVs) and die-to-die vias faces challenges related to on-chip circuitry for stacked devices.
Innovation Solution
The implementation of stacked memory devices with a stack position identifier (SPID) that allows each memory device to adjust its operations, such as self-refresh rate and latency, and connect internal signals through TSVs and die-to-die vias, enabling dynamic adaptation to any position in the stack without requiring different mask patterns or separate manufacturing/test lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertical stacking using TSVs and die-to-die vias is implemented, then memory density and I/O capacity are improved, but signal timing alignment and temperature management become more difficult
Solution Approach 1:
The patent applies preliminary action by pre-determining the stack position identifier (SPID) for each memory device before stacking. This allows each device to know its position in advance, enabling pre-configured signal timing adjustments and temperature management settings that compensate for the effects of stacking without requiring complex post-assembly calibration.
Solution Approach 2:
The patent changes parameters by adjusting signal timing and temperature management settings based on the SPID. Each memory device modifies its operational parameters according to its determined stack position, allowing the system to adapt to timing variations and thermal effects introduced by vertical stacking while maintaining overall system performance.
2Manufacturing precision
If different mask patterns and manufacturing/test lines are used for each stack position, then signal routing precision is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent applies universality by designing a single mask pattern and manufacturing process that can produce memory devices suitable for any stack position. The SPID determination circuitry and adaptive timing/temperature management features allow the same manufactured device to function correctly regardless of its position in the stack, eliminating the need for position-specific manufacturing variants.
Solution Approach 2:
The patent applies self-service by enabling each memory device to automatically determine its own stack position and adjust its operational parameters accordingly. The SPID determination and adaptive timing/temperature management features allow devices to self-configure based on their position, eliminating the need for external intervention or position-specific manufacturing processes.
3Manufacturing precision
If stack position identifier and adaptive timing adjustment circuitry are added, then signal timing alignment is improved, but on-chip circuitry complexity increases
Solution Approach 1:
The patent replaces mechanical/physical timing adjustment mechanisms with electronic/circuit-based solutions. Instead of using physical delay lines or mechanical switches to adjust timing, the invention uses electronic timing adjustment circuitry controlled by the SPID, which provides more precise and flexible timing alignment with reduced physical complexity.
Data Source
AI summary
Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal.