Stacked Memory Array Layout With Split Control Logic Optimization
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Solution Overview
Problem
Microelectronic device designers face challenges in reducing feature dimensions and increasing integration density while maintaining performance and simplifying fabrication, particularly due to processing conditions that limit control logic device configurations and performance in memory devices.
Innovation Solution
A method of forming microelectronic devices with a combination of cross-point and 3D NAND Flash memory architectures, including multiple control logic regions with different configurations, where a second control logic region and memory array are formed subsequent to the initial memory array, allowing for independent optimization of control logic devices and resistance variable memory cells without thermal budget constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory array is formed over base control logic structure using conventional processing conditions, then memory array can be fabricated, but control logic device configurations and performance are limited
Solution Approach 1:
The patent divides the control logic formation into separate stages: first forming an initial memory array with preliminary control logic, then subsequently forming additional control logic regions. This segmentation allows different control logic devices to be optimized independently without thermal budget constraints, resolving the contradiction between performance reliability and configuration adaptability.
Solution Approach 2:
The patent performs preliminary formation of the memory array and initial control logic structure before adding additional control logic regions. This preliminary action establishes a foundation that can later be enhanced without being constrained by the original processing conditions, enabling both performance improvement and configuration flexibility.
2Adaptability or versatility
If control logic devices are increased in quantity and complexity, then memory device functionality is enhanced, but device size (horizontal footprint) increases
Solution Approach 1:
The patent transitions from planar control logic layouts to three-dimensional vertically-stacked configurations. Control logic devices are stacked above and below the memory array, utilizing the vertical dimension to increase functionality and control capacity without expanding the horizontal footprint of the device.
Solution Approach 2:
The patent implements nested control logic regions where additional control logic devices are positioned within and around the memory array structure. This nesting approach allows multiple control logic functions to be integrated in a compact arrangement, enhancing functionality while minimizing device area.
3Quantity of substance
If feature dimensions are reduced and separation distance between features is reduced, then integration density is increased, but fabrication complexity and cost increase
Solution Approach 1:
The patent segments the fabrication process into distinct stages with different processing conditions. The initial memory array is formed under one set of conditions, then additional control logic regions are formed under different, optimized conditions. This segmentation allows each stage to be manufactured with appropriate process parameters, reducing overall fabrication complexity while achieving high integration density.
Solution Approach 2:
The patent changes processing parameters (temperature, pressure, materials) between different fabrication stages. By not being constrained to a single thermal budget, the process can optimize conditions for each specific structure being formed, simplifying manufacturing while achieving high density through advanced material deposition and patterning techniques.
Data Source
AI summary
A method of forming a microelectronic device comprises forming a microelectronic device structure comprising a first control logic region comprising first control logic devices, and a first memory array region vertically overlying the first control logic region and comprising an array of vertically extending strings of memory cells. An additional microelectronic device structure comprising a semiconductive material is attached to an upper surface of the microelectronic device structure. A portion of the semiconductive material is removed. A second control logic region is formed over the first memory array region. The second control logic region comprises second control logic devices and a remaining portion of the semiconductive material. A second memory array region is formed over the second control logic region. The second memory array region comprises an array of resistance variable memory cells. Microelectronic devices, memory devices, and electronic systems are also described.