Stacked Memory Truth Table Extension for SRAM Bandwidth Access
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Solution Overview
Problem
Memory bandwidth becomes a bottleneck in improving overall system performance as advancements in processing speed lead to increased demands in memory access times, particularly in stacked memory systems.
Innovation Solution
Implementing a truth table extension for stacked memory systems that allows direct access to a faster type of memory, such as SRAM, within a stack of DRAM, using modified command/address bus signals to enhance bandwidth without altering the existing package pinout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If processing speed is advanced to improve system performance, then processing capability is improved, but memory bandwidth becomes a bottleneck
Solution Approach 1:
The patent transitions from a single memory access dimension to multiple dimensions by enabling independent access to different memory types (DRAM and SRAM) within the stacked memory system. The command/address bus is extended to provide separate access paths, allowing the system to operate in multiple access dimensions simultaneously, thereby resolving the bandwidth bottleneck caused by single-dimension processing speed advancements.
Solution Approach 2:
The memory system is segmented into distinct memory types (DRAM and SRAM) that can be accessed independently through extended command/address bus signals. This segmentation allows different portions of the memory system to be accessed simultaneously with different protocols, increasing overall bandwidth and eliminating the bottleneck that would occur if all memory operations had to compete for a single access path.
2Productivity
If direct access to SRAM is implemented within DRAM stack, then bandwidth is enhanced, but device complexity increases
Solution Approach 1:
The command/address bus is designed with multi-functionality to handle both traditional DRAM operations and new SRAM access operations. By extending the existing bus to support multiple memory types and access modes, the system achieves universal compatibility without requiring separate dedicated buses for each memory type, thereby enhancing bandwidth while controlling the increase in device complexity.
Solution Approach 2:
The extended command/address bus acts as an intermediary that mediates between the processor and multiple memory types (DRAM and SRAM). This intermediary structure provides a unified interface that simplifies the complexity by abstracting the differences between memory types, allowing the processor to access both memory types through a single extended bus without requiring complex point-to-point connections for each memory type.
3Loss of time
If truth table extension is implemented to access faster memory, then access time is reduced, but command bus complexity increases
Solution Approach 1:
The truth table is extended partially rather than completely, adding only the specific signal combinations needed to access SRAM memory while maintaining compatibility with existing DRAM operations. This partial extension approach reduces access time for SRAM operations without requiring a complete redesign of the command bus protocol, thereby minimizing the increase in command bus complexity while achieving the time reduction benefit.
Data Source
AI summary
Techniques for extending a truth table of a stacked memory system are provided. In an example, a storage system can include a stack of first memory die configured to store data and a logic die. The logic die can include an interface circuit configured to receive multiple memory requests from an external host using a first command bus, a second command bus, and a data bus, and a controller configured to interface with the stack of first memory die to store and retrieve the data from the stack of first memory die. The logic die can include a second memory having a faster access time than devices of the stack of first memory die, and the interface circuit can directly access the second memory in response to a first memory request of the multiple of memory requests.