3D Stacked Memory Device with Staircase Contact Structure
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Solution Overview
Problem
Conventional nonvolatile semiconductor memory devices face challenges in increasing memory capacity due to difficulties in downsizing elements on a silicon substrate, particularly in forming effective contact structures for three-dimensional stacked memory configurations.
Innovation Solution
A semiconductor memory device is designed with a stacked body of alternately layered conductive and insulating layers, featuring memory holes with a charge storage film and a channel body, along with a staircase-shaped contact region and interconnection structure that facilitates electrical connections across the stacked body, allowing for miniaturization and efficient data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If elements are downsized on a silicon substrate to increase memory capacity, then memory capacity increases, but manufacturing difficulty and cost increase
Solution Approach 1:
The patent transitions from two-dimensional element arrangement on a silicon substrate to three-dimensional stacked memory structure. Multiple memory layers are stacked vertically, allowing memory capacity to increase in the vertical dimension rather than requiring further downsizing of elements in the planar dimension. This resolves the contradiction by enabling capacity expansion without proportionally increasing manufacturing difficulty associated with miniaturization.
Solution Approach 2:
The memory device is divided into multiple stacked layers, each containing memory cells. This segmentation allows the overall memory capacity to be distributed across several layers, with each layer being manufactured using standard processes. The segmentation approach avoids the need to manufacture a single ultra-dense layer, thereby reducing manufacturing difficulty while achieving high total capacity.
2Quantity of substance
If the number of stacked layers increases to increase memory capacity, then memory capacity increases, but forming contact structures becomes difficult
Solution Approach 1:
Contact holes are formed through the stacked layers before the interconnection layers are deposited. This preliminary formation of contact pathways simplifies subsequent interconnection formation, as the routing paths are already established. By performing this critical structuring step early in the manufacturing sequence, the complexity of forming reliable contacts through multiple layers is significantly reduced.
Solution Approach 2:
The contact holes are formed to pass through multiple stacked layers, with interconnection layers and insulation layers nested around the contact structures. This nested arrangement allows electrical connections to traverse through the vertical stack while maintaining proper insulation and connectivity at each level, managing the complexity of multi-layer contact formation.
3Quantity of substance
If elements are downsized to increase memory capacity, then memory capacity increases, but element dimension decreases making processing difficult
Solution Approach 1:
Instead of continuing to reduce element dimensions in the planar direction, the patent utilizes the vertical dimension by stacking multiple memory layers. Each layer can maintain larger, more easily manufacturable element dimensions while the overall device achieves high capacity through vertical integration. This approach preserves manufacturing precision requirements while still enabling capacity expansion.
Solution Approach 2:
The total memory capacity is segmented across multiple layers, each containing a manageable number of memory cells with dimensions suitable for standard manufacturing processes. This segmentation allows each layer to be processed with conventional precision requirements, avoiding the need for ultra-precise processing that would be required if all capacity were concentrated in a single ultra-dense layer.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a base, a stacked body, a memory film, a channel body, an interconnection, and a contact plug. The base includes a substrate and a peripheral circuit formed on a surface of the substrate. The stacked body includes a plurality of conductive layers and a plurality of insulating layers alternately stacked above the base. The memory film is provided on an inner wall of a memory hole punched through the stacked body to reach a lowermost layer of the conductive layers. The memory film includes a charge storage film. The interconnection is provided below the stacked body. The interconnection electrically connects the lowermost layer of the conductive layers in an interconnection region laid out on an outside of a memory cell array region and the peripheral circuit. The contact plug pierces the stacked body in the interconnection region to reach the lowermost layer of the conductive layers in the interconnection region.