Stacked Memory Structure With Staircase Contacts for Dense Gate Routing
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving high integration density due to the complexity of electrically connecting gate electrodes to peripheral circuits, which can lead to defects and inefficiencies.
Innovation Solution
A semiconductor device is designed with a stack structure that includes alternately stacked interlayer insulating layers and horizontal layers in both the memory cell array region and the connection region. This stack structure features a staircase region and a flat region in the connection area, with gate contact plugs and memory vertical structures to enhance integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacked gate electrodes is increased to achieve high integration density, then the integration density is improved, but the complexity of connecting gate electrodes to peripheral circuits increases and defects may occur
Solution Approach 1:
The patent transitions from vertical stacking alone to a combination of vertical stacking and horizontal extension. The stack structure extends horizontally into the connection region, creating a three-dimensional configuration that allows gate electrodes to connect to peripheral circuits in both vertical and horizontal directions, thereby reducing connection complexity while maintaining high integration density.
Solution Approach 2:
The stack structure is divided into distinct regions: a memory cell array region with vertically stacked gate electrodes and a connection region with horizontally extended gate pads. This segmentation allows the memory region to maintain high vertical integration while the connection region provides simplified horizontal access to peripheral circuits, resolving the contradiction between integration density and connection complexity.
2Ease of operation
If the stack structure extends into the connection region, then the connectivity to peripheral circuits is improved, but the manufacturing precision requirements increase due to the complex staircase and flat region structures
Solution Approach 1:
The stack structure exhibits different configurations in different regions: the memory cell array region contains vertically stacked gate electrodes for high-density storage, while the connection region contains horizontally extended gate pads for circuit connectivity. This local differentiation allows each region to be optimized for its specific function, improving connectivity without uniformly increasing manufacturing precision requirements across the entire device.
Solution Approach 2:
The stack structure partially extends into the connection region rather than fully extending or remaining entirely vertical. This partial extension creates the necessary horizontal connectivity while limiting the complexity of the staircase and flat regions, thereby balancing improved connectivity with manageable manufacturing precision requirements.
3Reliability
If the stack structure includes staircase and flat regions with multiple contact plugs, then the electrical connectivity is enhanced, but the number of manufacturing steps and potential defects increase
Solution Approach 1:
The stack structure serves multiple functions: vertical gate electrodes provide high-density storage in the memory region, while horizontally extended gate pads provide connectivity to peripheral circuits in the connection region. This multi-functionality allows a single structure to achieve both high reliability through improved connectivity and maintained manufacturing efficiency by avoiding the need for separate connection structures.
Data Source
AI summary
A semiconductor device includes a lower structure, a stack structure on the lower structure and extending from a memory cell region into a connection region, gate contact plugs on the stack structure in the connection region, and a memory vertical structure through the stack structure in the memory cell region, wherein the stack structure includes interlayer insulating layers and horizontal layers alternately stacked, wherein, in the connection region, the stack structure includes a staircase region and a flat region, wherein the staircase region includes lowered pads, wherein the flat region includes a flat pad region, a flat edge region, and a flat dummy region between the flat pad region and the flat edge region, and wherein the gate contact plugs include first gate contact plugs on the pads, flat contact plugs on the flat pad region, and a flat edge contact plug on the flat edge region.