Stacked Semiconductor Memory Sub-Block Erase Architecture
Solution Overview
Problem
Current semiconductor memory devices face challenges in achieving high memory efficiency and reducing manufacturing costs and size due to the complexity of erase operations and the increased number of through-chip vias and pass transistors required for higher memory capacities.
Innovation Solution
The semiconductor memory device architecture includes separate sub-blocks on different memory chips, allowing for independent application of erase voltage to each chip during erase operations, which reduces the size of the erase unit and improves memory efficiency without increasing the number of memory blocks or pass transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory chips are stacked to increase capacity, then memory capacity is improved, but device complexity increases due to multiple through-chip vias and pass transistors
Solution Approach 1:
The memory device is divided into multiple memory chips stacked vertically, with each chip containing separate sub-blocks. This segmentation allows independent erase operations on each chip, reducing the complexity of managing through-chip vias and pass transistors while maintaining high capacity through the stacked configuration.
Solution Approach 2:
The patent transitions from a planar layout to a three-dimensional stacked architecture. By organizing memory blocks across multiple vertical layers (chips), the design achieves higher capacity without proportionally increasing the complexity of erase operations, as each layer can be erased independently.
2Quantity of substance
If the number of memory blocks is increased to improve capacity, then memory capacity is improved, but erase operation complexity increases
Solution Approach 1:
Each memory chip is further divided into separate sub-blocks that can be independently selected and erased. This segmentation within chips allows the system to manage large total capacity through many small, independently erasable units, reducing the complexity of erase operations compared to managing large monolithic blocks.
Solution Approach 2:
The patent enables partial erase operations on specific sub-blocks rather than requiring complete chip erases. This partial action approach allows the system to erase only the necessary portions of memory, reducing the overall complexity and time required for erase operations while supporting high capacity through the stacked architecture.
3Ease of operation
If erase operations are performed on entire chips, then erase simplicity is maintained, but memory efficiency decreases due to larger erase units
Solution Approach 1:
The memory chips are segmented into separate sub-blocks that can be independently erased. This segmentation enables the system to maintain simple chip-level erase operations while also supporting efficient sub-block level erases, thereby improving memory efficiency by allowing smaller, more targeted erase operations without sacrificing operational simplicity.
Solution Approach 2:
The erase operation system is designed to be dynamic, allowing the controller to selectively erase either entire chips or individual sub-blocks based on the specific memory efficiency requirements. This dynamic capability enables the system to adapt between simple chip erases and efficient partial erases as needed.
Data Source
AI summary
A semiconductor memory device includes a plurality of first sub-blocks defined in a first memory chip; and a plurality of second sub-blocks defined in a second memory chip that is stacked on the first memory chip in a stack direction. Each of a plurality of memory blocks includes one of the plurality of first sub-blocks and one of the plurality of second sub-blocks, and wherein an erase voltage is separately applied to the first memory chip and the second memory chip in an erase operation, and the erase operation is performed in a sub-block.