Stacked Memory Substrate Layout for Higher 3D NAND Density
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Solution Overview
Problem
Existing semiconductor devices face challenges in increasing data storage capacity and integration density, particularly in three-dimensional arrangements of memory cells.
Innovation Solution
A semiconductor device design featuring stacked substrate structures with varying gate electrode lengths, channel structures, and input/output contact structures that enhance integration density by optimizing the arrangement of circuit and memory cell regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged three-dimensionally to increase data storage capacity, then storage capacity is improved, but device complexity increases
Solution Approach 1:
The semiconductor device is divided into two separate substrate structures: a first substrate structure containing circuit devices and a second substrate structure containing memory cell structures. This segmentation allows independent optimization of each substrate, reducing overall device complexity while maintaining high storage capacity through the three-dimensional arrangement of memory cells on the second substrate.
Solution Approach 2:
The memory cell structures on the second substrate are arranged in a three-dimensional configuration with gate electrodes extending in a second direction perpendicular to the first direction (which is perpendicular to the lower surface of the plate layer). This multi-dimensional arrangement maximizes storage capacity by utilizing vertical stacking and lateral extension, effectively increasing storage density without proportionally increasing device complexity.
2Quantity of substance
If gate electrodes are stacked vertically to increase integration density, then integration density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The gate electrodes are divided into two sets: first gate electrodes on the first substrate structure and second gate electrodes on the second substrate structure. This segmentation allows each set to be manufactured and optimized independently, reducing the cumulative precision requirements that would arise from manufacturing a single complex stacked structure, while still achieving high integration density through vertical stacking of the second gate electrodes on the second substrate.
Solution Approach 2:
The second gate electrodes are configured with varying lengths in the second direction, creating local variations in electrode characteristics. This local quality approach allows optimization of specific regions for different functions (e.g., longer electrodes for higher density, shorter electrodes for access regions), improving overall integration density while managing manufacturing precision through region-specific design rather than uniform constraints across the entire device.
3Volume of moving object
If substrate structures are stacked to reduce device size, then device size is reduced, but reliability challenges increase
Solution Approach 1:
The device is segmented into two independently optimized substrate structures that are stacked together. The first substrate structure contains circuit devices and the second substrate structure contains memory cell structures. This segmentation allows each substrate to be manufactured and tested separately, improving reliability by isolating potential failure modes, while the stacked configuration reduces overall device size through vertical integration.
Solution Approach 2:
Bonding metal layers are introduced as intermediary elements between the first and second substrate structures to establish electrical connections. These bonding metal layers serve as mediators that facilitate reliable inter-substrate connectivity, managing the reliability challenges inherent in stacked configurations by providing dedicated, optimized connection pathways between the two substrates while maintaining compact device dimensions.
Data Source
AI summary
A semiconductor device includes a first substrate structure including a substrate, circuit devices, and first bonding metal layers on the circuit devices, and a second substrate structure connected to the first substrate structure on the first substrate structure, wherein the second substrate structure includes a plate layer having a first region and a second region, gate electrodes stacked below the plate layer and extending by different lengths in a second direction in the second region, channel structures penetrating the gate electrodes and each including a channel layer, in the first region, input/output contact structures penetrating the plate layer and the gate electrodes and each including a contact conductive layer, in the second region, and second bonding metal layers connected to the first bonding metal layers, wherein a level of upper surfaces of the input/output contact structures is higher than a level of upper surfaces of the channel structures.