Vertically Stacked Memory Substrate Leakage Control
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Solution Overview
Problem
Non-volatile memory devices, such as flash memory, face issues with current leakage and unexpected programming due to voltage differences between stacked semiconductor substrates during erase operations, leading to inefficiencies and potential data corruption.
Innovation Solution
The implementation of vertically stacked semiconductor substrates with non-volatile memory cell transistors grouped into memory cell blocks, where specific voltage conditions are applied to each substrate to prevent current leakage and control programming operations, including applying a first voltage to one substrate for erase and a second voltage greater than 0V or floating the other substrate, and applying distinct voltages to transistors in different memory cell blocks to manage programming and erasing effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a high voltage is applied to the first semiconductor substrate for erase operation, then the erase efficiency is improved, but current leakage occurs to the second semiconductor substrate
Solution Approach 1:
A ground selection transistor is introduced as an intermediary component between the first and second semiconductor substrates. This transistor acts as a controlled switch that can be turned off during erase operations to block current leakage from the first substrate to the second substrate, while allowing normal operation when not performing erase. The ground selection transistor effectively mediates the electrical interaction between the two substrates, enabling high-voltage erase operations without unwanted current paths.
2Reliability
If voltage is applied to prevent current leakage, then reliability is improved, but device complexity increases due to additional voltage control requirements
Solution Approach 1:
Different voltage conditions are applied to different regions or substrates based on the specific operation being performed. During erase operations, the first substrate receives high voltage while the second substrate is held at a different voltage potential to prevent leakage. During normal operations, standard voltage conditions apply to both substrates. This localized voltage control ensures reliability only when needed, without permanently increasing device complexity.
Data Source
AI summary
Provided is a non-volatile memory device including first and second, vertically stacked semiconductor substrates, a plurality of non-volatile memory cell transistors formed in a row on the first and second semiconductor substrates, and a plurality of word lines connected to gates of the plurality of non-volatile memory cell transistors. The plurality of non-volatile memory cell transistors are grouped into two or more memory cell blocks, such that a first voltage is applied to the first semiconductor substrate including a first memory cell block to be erased, and either (1) a second voltage less than the first voltage and greater than 0V is applied to the second semiconductor substrate not including the first memory cell block, or (2) the second semiconductor substrate not including the first memory cell block is allowed to electrically float.