Stacked CPU-Accelerator Memory Circuit for Ternary Data Storage
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Solution Overview
Problem
The miniaturization and power efficiency of semiconductor devices are hindered by the increased number of transistors required for storing ternary data in SRAM, leading to higher heat generation and power consumption, particularly due to increased data transfer between the CPU and memory.
Innovation Solution
A semiconductor device architecture featuring a CPU and an accelerator with a memory circuit using metal oxide transistors for storage and silicon transistors for arithmetic operations, where data is switched between binary and ternary voltage levels, allowing for reduced transistor count and efficient data retention without power supply voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If ternary data is stored in an SRAM memory cell, then the data storage capability is improved, but the number of transistors in the memory cell increases
Solution Approach 1:
The patent transitions from planar 2D memory cell layout to 3D vertical stacking architecture. Multiple memory cells are stacked in the vertical dimension, allowing ternary data storage without proportionally increasing the transistor count in the planar footprint. This dimensional change enables higher storage density while controlling device complexity.
Solution Approach 2:
The memory cell design integrates multiple functions into a single structure that can store ternary data states. The circuit architecture enables the same memory cell to represent three distinct data states (typically through voltage levels or resistance states) without requiring separate dedicated circuits for each state, thereby improving storage capability without linearly increasing transistor count.
2Speed
If data is transferred frequently between CPU and memory, then the data access speed is improved, but the power consumption increases
Solution Approach 1:
The patent merges the CPU and memory into a tightly integrated unified architecture where memory is directly coupled to the processing unit. This integration reduces the physical distance and interface complexity between CPU and memory, enabling fast data access while minimizing the power required for data transfer through shorter interconnects and reduced signaling overhead.
Solution Approach 2:
The patent introduces an on-chip buffer or cache structure that acts as an intermediary between the CPU and main memory. This mediator layer holds frequently accessed data locally, reducing the need for repeated high-power transfers to and from external memory, thereby lowering overall power consumption while maintaining fast access speeds for common operations.
3Use of energy by moving object
If the circuit scale is reduced using BNN or TNN architectures, then the power consumption is reduced, but the manufacturing precision requirements increase
Solution Approach 1:
The patent employs BNN (Binary Neural Network) or TNN (Ternary Neural Network) architectures that change the data representation parameters from conventional multi-bit formats to binary or ternary states. This parameter change reduces the circuit scale and power consumption by simplifying logic operations and reducing the number of transistors required, while the design incorporates error tolerance mechanisms to manage manufacturing variations.
Solution Approach 2:
The patent incorporates error correction codes, redundancy, or tolerance-based design approaches that cushion against manufacturing precision variations. By designing the system to anticipate and compensate for fabrication tolerances beforehand, the reduced circuit scale achieved through BNN/TNN can be manufactured with acceptable yield despite relaxed precision requirements.
Data Source
AI summary
A semiconductor device having a novel structure is provided. The semiconductor device includes a CPU and an accelerator. The accelerator includes a first memory circuit and an arithmetic circuit. The first memory circuit includes a first transistor. The first transistor includes a semiconductor layer containing a metal oxide in a channel formation region. The arithmetic circuit includes a second transistor. The second transistor includes a semiconductor layer containing silicon in a channel formation region. The first transistor and the second transistor are provided to be stacked. The CPU includes a CPU core including a flip-flop provided with a backup circuit. The backup circuit includes a third transistor. The third transistor includes a semiconductor layer containing a metal oxide in a channel formation region.