Stacked Memory Die Bonding for Semiconductor Thermal Mitigation
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Solution Overview
Problem
Conventional semiconductor device packaging techniques face challenges in achieving effective thermal mitigation due to the limitations of non-conductive filling materials with low thermal conductivity, which hinder the production of large stacks of semiconductor dies.
Innovation Solution
The implementation of wafer-to-wafer front-to-back side bonding between dummy silicon dies and stacked semiconductor dies, using a second dielectric layer for dielectric-dielectric fusion bonding, which provides a thinner and more thermally conductive interface compared to conventional non-conductive filling materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If non-conductive filling materials are used to encapsulate semiconductor dies, then the dies are protected from environmental factors, but thermal conductivity is reduced and thermal mitigation is hindered
Solution Approach 1:
The patent employs a composite material structure where a thermally conductive underfill material with higher thermal conductivity than the encapsulant material is placed between the semiconductor die and substrate. This composite approach allows the encapsulant to provide environmental protection while the underfill layer specifically addresses thermal conduction, resolving the contradiction between protection and heat dissipation.
Solution Approach 2:
The patent applies different material properties to different regions: the encapsulant material provides environmental protection in the bulk, while the thermally conductive underfill material is localized at the interface between the die and substrate where heat generation occurs. This local differentiation of material quality enables simultaneous achievement of protection and thermal management.
2Ease of manufacture
If conventional packaging processes are used, then manufacturing is simplified, but thermal mitigation performance is insufficient for large stacks of semiconductor dies
Solution Approach 1:
The packaging structure is segmented into distinct functional layers: an encapsulant material for environmental protection and a separate thermally conductive underfill material for heat dissipation. This segmentation allows each layer to be optimized for its specific function while maintaining compatibility with conventional packaging processes, enabling improved thermal performance without sacrificing manufacturing simplicity.
3Stability of the object's composition
If thick interface materials are used between semiconductor dies, then mechanical stability is improved, but thermal conductivity is reduced due to increased thermal resistance
Solution Approach 1:
The patent changes the thermal conductivity parameter of the interface material by selecting an underfill material with significantly higher thermal conductivity than conventional encapsulants. This parameter change enables the interface material to maintain mechanical stability while simultaneously reducing thermal resistance, allowing efficient heat transfer through the die stack.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances thermal mitigation performance by increasing the thermal conductivity and reducing the thickness of the interface material, allowing for better heat management in stacked semiconductor devices.
Implementation Method 1
the second dielectric layer having dielectric-dielectric fusion bonding... increasing the thermal conductivity and reducing the thickness of the interface material, allowing for better heat management
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes a logic die, a first plurality of stacked memory dies electrically coupled with the logic die at a first location above a back side surface of the logic die, a second plurality of stacked memory dies electrically coupled with the logic die at a second location above the back side surface of logic die, a first dielectric material disposed above the back side surface of the logic die and between the first plurality of stacked memory dies and the second plurality of stacked memory dies, and a dummy die disposed above the first dielectric material and coupled to the first plurality of stacked memory dies and the second plurality of stacked memory dies, wherein the dummy die is coupled to back side surfaces of the first plurality and second plurality of stacked memory dies through a second dielectric layer having dielectric-dielectric fusion bonding.