Stacked Memory Array Integration Beyond Control Logic Thermal Limits
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Solution Overview
Problem
Conventional microelectronic device designs, particularly in memory devices, face challenges in reducing size and improving performance due to limitations in control logic device configurations and processing conditions, which impede miniaturization and performance enhancements such as faster memory cell switching, lower power consumption, and higher data transfer rates.
Innovation Solution
The method involves forming a microelectronic device structure with a memory array region over a semiconductive base structure, attaching it to a base structure, removing a portion of the base structure to create a control logic region, and forming control logic devices in electrical communication with the memory array, allowing for independent configuration of control logic without thermal budget constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If control logic devices are formed under the same processing conditions as memory array formation, then manufacturing process is simplified, but control logic device configurations and performance are limited
Solution Approach 1:
The patent divides the device into two separate structures: a memory array structure formed first, then a control logic structure formed separately and attached to it. This segmentation allows each structure to be optimized independently under its own processing conditions, resolving the contradiction between manufacturing simplicity and configuration flexibility.
Solution Approach 2:
The patent transitions from a planar co-formed structure to a three-dimensional stacked architecture where the control logic structure is attached vertically to the memory array structure. This dimensional change enables independent processing of each structure while maintaining electrical connection, achieving both manufacturing ease and design flexibility.
2Reliability
If control logic devices are formed before memory array attachment, then thermal budget constraints limit performance, but forming them after attachment adds process complexity
Solution Approach 1:
The memory array structure is formed completely first with all its required processing, then the control logic structure is formed separately and attached. This preliminary action allows the memory array to be optimized without thermal constraints from subsequent control logic formation, while the added attachment process is justified by the performance gains.
3Ease of manufacture
If conventional planar arrangements of transistors are used, then fabrication is simpler, but integration density and performance are reduced
Solution Approach 1:
The patent transitions from two-dimensional planar transistor arrangements to three-dimensional vertical stacking where memory strings extend vertically through multiple decks. This dimensional change dramatically increases integration density while maintaining fabrication simplicity through standardized vertical processing techniques.
Data Source
AI summary
A method of forming a microelectronic device comprises forming a microelectronic device structure. The microelectronic device structure comprises a semiconductive base structure, and a memory array region vertically overlying the semiconductive base structure and comprising memory cells. The microelectronic device structure is attached to a base structure. A portion of the semiconductive base structure is removed after attaching the microelectronic device structure to a base structure. A control logic region is formed vertically over a remaining portion of the semiconductive base structure. The control logic region comprises control logic devices in electrical communication with the memory cells of the memory array region. Microelectronic devices, memory devices, electronic systems, and additional methods are also described.