3D Semiconductor Memory Interconnects With Localized Thick Contact Layers
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in achieving high integration and capacity while maintaining efficient data storage and retrieval operations, particularly in three-dimensional memory structures.
Innovation Solution
The semiconductor memory device employs a stacked interconnect structure with specific conductive and insulator portions arranged to optimize the layout and connectivity of memory pillars and conductive layers, enhancing the efficiency and capacity of data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a three-dimensional memory structure is employed for high integration and high capacity, then storage capacity increases, but manufacturing complexity and process difficulty increase
Solution Approach 1:
The conductive layers are divided into first portions and second portions with different thicknesses and functions. The second portions extend beyond the upper conductive layers to form contact regions, segmenting the interconnect structure into functional zones that simplify the manufacturing process while maintaining high storage capacity
Solution Approach 2:
The conductive layers transition from a two-dimensional planar structure to a three-dimensional stacked structure with vertical extensions. The second portions of conductive layers protrude in the vertical direction to contact upper layers, adding a dimensional aspect that reduces manufacturing complexity while preserving high density
2Reliability
If conductive layers are made thicker to improve signal integrity, then electrical performance improves, but area occupied by conductive layers increases
Solution Approach 1:
The conductive layers have different thicknesses at different locations: first portions have a first thickness for general conduction, while second portions have a greater second thickness for contact and signal integrity. This local variation in thickness optimizes electrical performance without increasing the overall planar area
Solution Approach 2:
Instead of increasing thickness uniformly across the entire conductive layer area, the invention uses vertical extensions of the second portions to achieve the necessary electrical performance. This dimensional approach maintains compact planar footprint while ensuring signal integrity through thicker contact regions
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a plurality of conductive layers, each of the plurality of conductive layers including a first portion, and a second portion that is thicker than the first portion, a first insulator portion that contacts the second portion of a first conductive layer and the second portion of a second conductive layer, and a second insulator portion that contacts the second portion of a third conductive layer, wherein the second portion of the second conductive layer includes a first sub portion arranged with the second portion of the first conductive layer, and a second sub portion provided between the second portion of the first conductive layer and the second portion of the third conductive layer.