Stacked Semiconductor Memory Through Vias Noise Reduction
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Solution Overview
Problem
In semiconductor memory devices with multiple stacked chips, high resistance in voltage signal paths leads to increased noise intensity, degrading memory operating characteristics and chip performance, especially when chips are densely packed on a small area.
Innovation Solution
The implementation of dedicated, electrically isolated supply voltage paths for each chip within the semiconductor memory device, using through vias that are specifically aligned and connected to prevent overlap and reduce noise interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor chips are stacked within one semiconductor memory device to increase capacity, then the memory capacity increases, but the resistance in voltage signal paths increases leading to higher noise intensity
Solution Approach 1:
The patent divides the voltage signal paths into separate dedicated paths for each chip. Through vias are selectively formed in master chips to create independent voltage supply routes, segmenting the originally shared path into multiple isolated paths that reduce noise interference between chips while maintaining high capacity.
Solution Approach 2:
The patent applies different via formation strategies to different chips based on their roles. Master chips have through vias formed to create dedicated voltage paths, while slave chips use existing paths. This local differentiation optimizes noise reduction where most needed (in master chips with higher resistance) while maintaining overall system efficiency.
2Quantity of substance
If chips are densely packed on a small area to increase capacity, then the memory capacity increases, but the resistance in voltage signal paths increases leading to degraded memory operating characteristics
Solution Approach 1:
The patent transitions from planar to three-dimensional stacking architecture. By forming through vias that extend vertically through multiple stacked chips, the invention creates dedicated voltage paths in the vertical dimension, effectively reducing path resistance and noise interference while maintaining high density packing in the horizontal plane.
3Device complexity
If a single shared path is used for supply voltage to multiple chips, then the device complexity is reduced, but the noise intensity increases degrading chip performance
Solution Approach 1:
The patent segments the shared voltage path into multiple dedicated paths by selectively forming through vias in master chips. This segmentation creates electrically isolated routes for each chip, reducing noise interference while maintaining relatively simple overall device structure through the systematic via formation approach.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces noise-induced degradation in memory performance by ensuring separate and dedicated voltage paths for each chip, enhancing the reliability and efficiency of memory operations in densely packed semiconductor memory devices.
Implementation Method 1
a first through via, the first through via passing through the first master chip and electrically connected to the first master chip to provide a supply voltage to the first master chip
Implementation Method 2
If higher resistance occurs in this path, the intensity of noise generated in the supply or ground voltage transferred to each of the semiconductor chips also increases
Data Source
AI summary
A memory module includes a first multichip package including a first master chip and a first plurality of slave chips, and a second multichip package, the second multichip package including a second master chip and a second plurality of slave chips. A first through via passes through the first master chip and electrically connects to the first master chip to provide a supply voltage to the first master chip. A second through via passes through the first master chip without being electrically connected to provide a supply voltage to the first master chip. A first set of additional through vias pass through respective ones of the first plurality of slave chips and electrically connect to the respective ones of the first plurality of slave chips, wherein the second through via and first set of additional through vias are aligned to form a first stack of through vias.