Stacked Memory Tile Timing Adjustment for Uniform Signal Paths
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Solution Overview
Problem
The design and construction of stacked semiconductor devices with multiple memory tiles controlled by a single logic chip are complicated due to difficulties in achieving uniform signal path characteristics and output delays, leading to increased complexity and size.
Innovation Solution
Incorporation of timing adjustment devices, including selectors and flip-flops, in each memory tile to adjust setup and hold times for input signals and output data relative to the clock signal, allowing for flexible design and uniform signal characteristics across multiple memory tiles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If a single logic chip controls multiple memory tiles, then the device can be miniaturized, but the design complexity increases due to different signal path lengths
Solution Approach 1:
The patent applies local quality by providing different wire tree structures for different memory tiles based on their positions relative to the logic chip. Memory tiles at different locations receive customized wiring configurations to compensate for varying signal path lengths, allowing each tile to have optimal timing characteristics while maintaining overall device miniaturization.
Solution Approach 2:
The patent changes the parameter of wire tree structure configuration for each memory tile based on its position. By adjusting the wiring architecture parameter locally for each tile, the system maintains uniform signal characteristics across all tiles despite different physical distances from the logic chip, thus reducing design complexity while enabling smaller device volume.
2Manufacturing precision
If wire tree structures are designed to equalize signal paths, then timing uniformity is achieved, but the logic chip size increases
Solution Approach 1:
Instead of applying a uniform wire tree structure to all memory tiles, the patent provides localized custom wiring for each tile based on its position. This approach achieves timing uniformity by addressing the specific signal path requirements of each tile without requiring a monolithic redesign of the entire logic chip, thus avoiding the need to increase logic chip area.
Solution Approach 2:
The patent segments the wire tree structure design into tile-specific configurations rather than a single unified structure. Each memory tile receives a customized wire tree based on its position, which allows timing uniformity to be achieved through localized adjustments rather than requiring a comprehensive increase in logic chip area.
3Manufacturing precision
If multiple logic memory controllers are used, then signal path length differences are reduced, but the device complexity and size increase
Solution Approach 1:
The patent segments the control function by providing customized wire tree structures for each memory tile based on its position, rather than using multiple logic memory controllers. This segmentation approach achieves uniform signal path characteristics by addressing each tile's specific timing requirements individually, avoiding the complexity and size increase that would result from implementing multiple controllers.
Solution Approach 2:
The patent changes the wire tree structure parameter for each memory tile based on its position relative to the logic chip. By adjusting this parameter locally for each tile, the system achieves uniform signal path characteristics without needing to introduce additional controllers, thus avoiding the associated complexity and size penalties.
Data Source
AI summary
A stacked memory with a timing adjustment function is provided, including a logic chip; a memory chip coupled to the logic chip in a face-to-face manner and including plural memory tiles; plural timing adjustment devices, respectively provided in each memory tile, wherein for each memory tile, each timing adjustment device further includes a first timing adjustment device that is configured to adjust setup times and hold times for a command and an address with respect to an edge of a clock signal and a second timing adjustment device that is configured to adjust a setup time and a hold time for input data with respect to the edge of the clock signal.