3D Stacked Memory Transistor Structure for High Density
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Solution Overview
Problem
Current three-dimensional memory arrays face challenges in efficiently utilizing available layers and practical difficulties in manufacturing due to alignment issues, leading to high production tolerances and complexity in achieving increased cell density for mass storage applications.
Innovation Solution
A transistor and memory cell structure utilizing a stack of layers with a silicon substrate, thick oxide layer, bulk region, conduction region, gate oxide region, and gate region, where the bulk and conduction regions form a channel, and the gate region acts as a control element, allowing for pinch-off of the channel by applying voltages to either the gate or bulk region, enabling flexible control and compact design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional memory arrays are formed by superimposed levels of cells to increase storage capacity, then the storage density is improved, but the alignment precision and manufacturing complexity deteriorate
Solution Approach 1:
The patent transitions from traditional planar two-dimensional memory arrays to three-dimensional stacked memory structures. Multiple levels of memory cells are superimposed vertically, with each level containing memory cells formed by the intersection of bit lines and word lines. This dimensional change enables increased storage capacity by utilizing the vertical space above the substrate, thereby improving storage density without being constrained by planar area limitations.
Solution Approach 2:
The three-dimensional memory array is segmented into multiple discrete levels stacked above the substrate. Each level is independently formed with its own set of bit lines, word lines, and memory cells. This segmentation allows for modular manufacturing where each level can be processed and aligned separately, then stacked together. The segmentation approach helps manage the complexity of three-dimensional fabrication by breaking it down into repeatable unit processes.
2Quantity of substance
If three-dimensional memory arrays with multiple levels are implemented to increase cell density, then the cell density is improved, but the device complexity increases
Solution Approach 1:
The patent employs universal structural elements and processing techniques that can be repeated across all levels of the three-dimensional memory array. The same basic cell structure, formed by intersecting bit lines and word lines, is used at each level. This universality allows for standardized manufacturing processes to be applied repeatedly, reducing the overall device complexity despite the increased number of levels. The modular nature of the structure enables systematic scaling without proportionally increasing complexity.
3Ease of manufacture
If conventional planar memory structures are used to maintain simple manufacturing, then the ease of manufacture is improved, but the storage capacity is limited
Solution Approach 1:
The patent overcomes the storage capacity limitations of planar structures by transitioning to three-dimensional stacked architecture. Multiple levels of memory cells are formed vertically above the substrate, effectively utilizing the z-dimension for storage. This dimensional change enables significant increases in storage capacity while maintaining manufacturing processes that are extensions of conventional planar techniques, such as sequential deposition and patterning of conductive and dielectric layers.
Solution Approach 2:
The three-dimensional memory structure implements a nested arrangement where multiple levels of memory cells are stacked one above another, with each level nested within the vertical space defined by the levels below and above it. The substrate and lower levels provide structural support and electrical connections for the upper levels, creating a nested hierarchy. This nesting approach maximizes the use of available vertical space, thereby increasing storage capacity without requiring proportional increases in lateral footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This structure allows for a compact, flexible, and efficient design that can be used in both two-dimensional and three-dimensional arrays, overcoming alignment issues and achieving high cell density while maintaining manufacturing feasibility and reliability.
Implementation Method 1
A transistor and memory cell structure utilizing a stack of layers with a silicon substrate, thick oxide layer, bulk region, conduction region, gate oxide region, and gate region, where the bulk and conduction regions form a channel, and the gate region acts as a control element, allowing for pinch-off of the channel by applying voltages to either the gate or bulk region
Data Source
AI summary
Semiconductor device formed by a first conductive strip of semiconductor material; a control gate region of semiconductor material, facing a channel portion of the first conductive strip, and an insulation region arranged between the first conductive strip and the control gate region. The first conductive strip includes a conduction line having a first conductivity type and a control line having a second conductivity type, arranged adjacent and in electrical contact with each other, and the conduction line forms the channel portion, a first conduction portion and a second conduction portion arranged on opposite sides of the channel portion.