Multi-Deck Memory Transistor Configuration for Routing and Area Limits
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Solution Overview
Problem
As memory devices scale with multiple layers of memory arrays, the limited substrate area poses challenges for substrate-based circuitry, leading to increased area utilization and routing issues, limiting the ability to support a growing quantity of decks and associated circuitry.
Innovation Solution
Implementing substrate-based circuitry in multiple levels, with both lower and upper substrate-based circuitry formed by doping portions of respective substrates, allowing circuitry to be distributed above and below the stack of memory cells, thereby increasing the available area for circuitry and alleviating routing challenges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If substrate-based circuitry is implemented in multiple levels with circuitry distributed above and below the stack of memory cells, then the available area for circuitry is increased and routing challenges are alleviated, but the device complexity is increased
Solution Approach 1:
The patent applies dimensionality change by transitioning from a single-level substrate-based circuitry architecture to a multi-level architecture where circuitry is distributed both above and below the stack of memory cells. This vertical distribution across multiple levels effectively increases the available area for circuitry without expanding the horizontal footprint, thereby resolving the area constraint while managing complexity through structured spatial organization.
2Quantity of substance
If memory devices scale with multiple layers of memory arrays, then the storage capacity is increased, but the limited substrate area leads to increased area utilization and routing issues
Solution Approach 1:
The patent resolves the substrate area limitation by utilizing the vertical dimension to distribute circuitry across multiple levels above and below the memory cell stack. This approach enables scaling of storage capacity through additional memory layers without proportionally increasing the substrate footprint, as circuitry is efficiently organized in the vertical dimension rather than consuming excessive horizontal space.
Solution Approach 2:
The patent applies segmentation by dividing the substrate-based circuitry into multiple distinct levels or segments distributed vertically. Instead of concentrating all circuitry on a single substrate level, the circuitry is segmented across upper and lower levels, allowing each segment to be optimized independently and reducing routing congestion that would arise from dense single-level integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables greater scaling of memory devices by supporting a larger number of decks within a given footprint, improving area utilization and routing flexibility, and enabling more efficient operation of memory arrays.
Implementation Method 1
a first plurality of transistors formed at least in part by doping portions of a first semiconductor substrate
Data Source
AI summary
Methods, systems, and devices for transistor configurations for multi-deck memory devices are described. A memory device may include a first set of transistors formed in part by doping portions of a first semiconductor substrate of the memory device. The memory device may include a set of memory cells arranged in a stack of decks of memory cells above the first semiconductor substrate and a second semiconductor substrate bonded above the stack of decks. The memory device may include a second set of transistors formed in part by doping portions of the second semiconductor substrate. The stack of decks may include a lower set of one or more decks that is coupled with the first set of transistors and an upper set of one or more decks that is coupled with the second set of transistors.