Stacked Memory Cells with Trench Capacitors for Multi-Bit Reading
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Solution Overview
Problem
Current memory devices face challenges in reading multi-bit data efficiently, requiring longer times and higher power consumption due to sequential data retrieval from multiple memory cells, which also increases the circuit area and manufacturing costs.
Innovation Solution
A memory device structure where selection signals are concurrently transmitted to multiple memory cells with capacitors of different capacitance values, allowing for simultaneous data reading, reducing the reading time and power consumption, and enabling a smaller circuit area with a lower manufacturing cost by using a stacked-layer structure with trench capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If sequential reading from multiple memory cells is performed, then data is read from each memory cell in turn, but the reading time increases and power consumption increases
Solution Approach 1:
Multiple memory cells are merged into a single memory block structure where capacitors from different memory cells are connected to a common bit line through transistor control. This allows simultaneous reading of multi-bit data from multiple memory cells by combining their output signals, thereby reducing the total reading time while maintaining data integrity.
Solution Approach 2:
The memory device employs dynamic control of transistor switching states to enable selective connection of different capacitor groups to the bit line. By dynamically adjusting transistor gate voltages, the system can concurrently access multiple memory cells and switch between different reading modes, improving overall reading efficiency and reducing time loss.
2Use of energy by stationary object
If multiple memory cells are accessed sequentially, then each memory cell is read one by one, but power consumption increases
Solution Approach 1:
The patent combines multiple memory cell outputs into a single reading operation by connecting capacitors from different memory cells to a common bit line. This merging approach allows simultaneous data retrieval from multiple cells, reducing the cumulative power consumption that would result from sequential access while maintaining high data retrieval efficiency.
Solution Approach 2:
The memory device performs preliminary setup of transistor switching states and capacitor connections before the actual reading operation. By pre-configuring the circuit state, the system can execute concurrent reading operations without the overhead of repeated setup procedures, thereby reducing power consumption while maintaining high productivity.
3Area of stationary object
If conventional memory structure is used, then circuit area is larger and manufacturing cost is higher, but multi-bit data reading is not achieved
Solution Approach 1:
The patent transitions from a planar memory cell arrangement to a stacked-layer structure where capacitors are positioned in different vertical layers. This dimensional change allows multiple memory cells to share the same footprint area, significantly reducing the overall circuit area while enabling concurrent multi-bit data reading through selective activation of transistors in different layers.
Solution Approach 2:
The memory block is designed with universal transistor and capacitor structures that can serve multiple functions. The same basic memory cell design can be configured to read different bits of data by controlling which transistors are activated, providing multi-bit data reading capability without requiring separate dedicated circuits for each bit, thereby reducing overall circuit area and manufacturing complexity.
Data Source
AI summary
A memory device capable of reading multi-bit data at a time is provided. The memory device includes a first layer and a second layer positioned above or below the first layer. The first layer includes a first transistor and a first capacitor, and the second layer includes a second transistor and a second capacitor. Each of the first and second capacitors is a trench capacitor, and the trench length of the second capacitor is larger than the trench length of the first capacitor. A voltage retained in the first capacitor corresponds to a lower bit signal of data, and a voltage retained in the second capacitor corresponds to a higher bit signal of the data.