Stacked Memory System with TSV Interconnects and Controller
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Solution Overview
Problem
Conventional information processing devices require multiple types of memories due to differences in operating frequency and data bus width between main and sub-memory systems, leading to increased component and production costs.
Innovation Solution
A memory system with multiple memory chips connected via address, data, and control buses in a stacked arrangement, utilizing through-silicon vias (TSVs) for inter-chip connections and a memory controller to manage chip select signals, allowing for unified data and address signal processing across processors and memory chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If separate memory systems are used for main system and subsystem, then each system can operate at its optimal speed and bus width, but component cost and production cost increase
Solution Approach 1:
The patent applies universality by enabling a single memory chip to serve multiple functions: it can be accessed by both the main system and subsystem, and can operate in different modes (first mode for main system access, second mode for subsystem access). This eliminates the need for separate memory systems while maintaining optimal performance for each system type.
Solution Approach 2:
The patent implements dynamics through the memory control device that dynamically switches the memory chip between different operating modes based on which system (main or subsystem) needs to access the memory. The memory chip can flexibly change its operating characteristics to match the requirements of the accessing system.
2Area of moving object
If separate memory systems are used for main system and subsystem, then each system can operate at its optimal bus width, but wiring complexity and production cost increase
Solution Approach 1:
The memory chip is designed to universally interface with both main system and subsystem, accepting data bus widths from either system and internally managing the data transfer. This eliminates the need for separate memory systems with different bus widths, simplifying manufacturing while maintaining optimal bus width characteristics for each system.
Solution Approach 2:
The memory control device acts as an intermediary between the memory chip and the two systems. It receives data from either the main system or subsystem, manages the data bus width conversion if needed, and forwards it to the memory chip, thereby enabling a single memory system to handle different data bus widths without requiring separate memory systems.
3Device complexity
If a single memory chip is shared between main system and subsystem, then component cost and wiring cost are reduced, but access conflicts may occur
Solution Approach 1:
The memory control device implements periodic action by alternating between granting access to the main system and the subsystem in time-divided manner. It periodically switches between first mode (main system access) and second mode (subsystem access), ensuring that both systems can access the memory chip reliably without conflicts through time-division multiplexing.
Data Source
AI summary
A memory system method for controlling the same, and an information processing device using the same are provided. The system includes a plurality of memory chips electrically connected with one another by a bus (e.g. address bus, data bus, control bus, etc.), which are disposed in a stacked arrangement and extend through the plurality of memory chips in a stacking direction, and a memory controller connected to a plurality of processors and to the bus, and further to a chip select signal line for outputting a chip select signal to each of the plurality of memory chips. The memory controller converts an address signal from each of the processors into a set of the chip select signal and the address signal, which is outputted to the address bus, so as to relay inputs and outputs of data between each of the processors and each of the memory chips.