Stacked Memory Chip TSV Interconnects with Shared Electrodes
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor memory devices face challenges in efficiently integrating and managing different types of memory chips, such as DRAM and flash memory, within a single package, leading to complexities in data storage and management, and increased size and power consumption of memory controllers due to the need for separate signal paths and electrodes.
Innovation Solution
A semiconductor memory device design that stacks multiple DRAM and flash memory chips, using through-silicon vias (TSVs) for electrical coupling and shared external connection electrodes, with chip select signals and slice identification information enabling independent access and operation of each chip, allowing for different timing and efficient data management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple different types of memory chips are integrated within a single package, then memory functionality and storage capacity are improved, but device complexity and control difficulty increase
Solution Approach 1:
The memory package is segmented into multiple independent memory chip stacks, where each stack contains memory chips of the same type (e.g., DRAM or flash memory) coupled through dedicated TSVs. This segmentation allows each stack to be controlled independently, reducing the overall control complexity while maintaining versatile memory functionality.
Solution Approach 2:
TSVs (through-silicon vias) serve as intermediary structures that enable electrical coupling between memory chips within each stack. By using TSVs as intermediaries, the patent simplifies the interconnection architecture and reduces the complexity of signal routing between different memory chip types.
2Reliability
If separate signal paths and electrodes are used for different memory chip types, then signal integrity is improved, but the number of external electrodes and device size increase
Solution Approach 1:
The patent merges the signal paths of multiple memory chip types by routing them through shared external connection electrodes. Different memory chip stacks (DRAM and flash memory) share common electrodes while maintaining electrical independence through internal TSV coupling, thereby reducing the total number of external electrodes required and minimizing package size.
Solution Approach 2:
External connection electrodes are designed with multi-functionality, serving as common connection points for multiple different types of memory chips. This universal electrode design allows a single electrode to interface with multiple memory stacks, reducing the overall electrode count while maintaining signal integrity through proper internal routing and isolation.
3Speed
If multiple memory chips are electrically coupled through TSVs, then data access speed is improved, but manufacturing complexity increases
Solution Approach 1:
The electrical coupling architecture is segmented into discrete TSV structures that connect memory chips in a systematic, modular fashion. Each TSV array connects specific memory chips within a stack, creating a repeatable manufacturing pattern that reduces overall manufacturing complexity despite the high-speed interconnections.
Solution Approach 2:
The patent optimizes TSV parameters such as diameter, depth, and spacing to achieve high-speed data access while maintaining manufacturability. By carefully controlling these geometric parameters, the design balances performance requirements with manufacturing capabilities, enabling fast data access through TSVs without excessive manufacturing complexity.
Data Source
AI summary
A semiconductor memory device may include a plurality of memory chips stacked upon one another, and electrically coupled to one another through a plurality of first TSVs. The semiconductor memory device may include a plurality of second memory chips stacked separately from the first memory chips, and the plurality of second memory chips electrically coupled to one another through a plurality of second TSVs. The semiconductor memory device may include a plurality of external connection electrodes coupled to both to the first memory chips and the second memory chips. Wherein one of the first and second memory chips may be accessed in response to chip select signals inputted through the external connection electrodes.