Stacked Memory TSV Switching for Redundant Signal Paths
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Solution Overview
Problem
Existing memory devices face challenges in improving yield and reliability due to potential connection failures in through-silicon vias (TSVs) used for inter-chip communication, which can lead to chip failures and reduced performance.
Innovation Solution
Incorporation of a TSV switching circuit that allows switching between default and redundant vias for signal communication, ensuring that if a default via fails, the redundant via can be utilized, thereby maintaining communication pathways and enhancing the reliability and yield of the memory device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If default vias are used for inter-chip communication, then device complexity is reduced, but reliability deteriorates due to potential connection failures
Solution Approach 1:
The patent pre-configures redundant vias alongside default vias during manufacturing, but keeps them inactive initially. The switching circuit is pre-built to enable rapid activation of redundant vias only when needed, based on test results or failure detection, thus maintaining simplicity during normal operation while ensuring reliability when required.
Solution Approach 2:
The patent implements a dynamic switching mechanism that allows the system to transition from using only default vias to activating redundant vias based on detected connection failures. The switching circuit dynamically reconfigures the communication path between chips by changing via selection based on operational status, optimizing the balance between complexity and reliability.
2Reliability
If redundant vias are incorporated into the memory device, then reliability is improved through alternative communication paths, but device complexity increases
Solution Approach 1:
The patent introduces a switching circuit as an intermediary component that manages the selection between default and redundant vias. This mediator abstracts the complexity of having multiple via paths, presenting a simple interface to the rest of the system while handling the complex routing logic internally, thus isolating complexity to a dedicated control component.
Solution Approach 2:
The patent divides the via system into separate functional groups: default vias for normal operation and redundant vias for failure compensation. The switching circuit segments the control logic to independently manage each via type, allowing the system to activate only the necessary subset of vias based on operational needs, thereby reducing the effective complexity at any given time.
3Adaptability or versatility
If switching circuits are added to enable via switching, then adaptability is improved through dynamic path selection, but device complexity increases
Solution Approach 1:
The switching circuit and control logic are designed and integrated during the manufacturing process, with via selection patterns predetermined based on expected failure modes. Test procedures are pre-configured to identify functional vias before deployment, allowing the system to adapt to actual via status without requiring complex runtime decision-making, thus reducing operational complexity while maintaining adaptability.
Data Source
AI summary
According to one embodiment, a memory device includes a first chip, a second chip stacked above the first chip, and a switching circuit. The second chip includes a substrate, a memory cell array, and first to third vias each passing through the substrate and connected to the first chip. The switching circuit is configured to switch among: a first state in which, between the first and second chips, first and second signals are communicated through the first and second vias respectively; a second state in which, between the first and second chips, the first and second signals are communicated through the third and second vias respectively; and a third state in which, between the first and second chips, the first and second signals are communicated through the first and third vias respectively.