Stacked Memory Vault Interface for High-Bandwidth HMC Control

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Solution Overview

Problem

Current memory technologies fail to provide sufficient memory bandwidth and density to meet the demands of high-performance computing and graphics processing units, leading to performance bottlenecks in systems that require tightly coupled memory solutions.

Innovation Solution

The implementation of a hybrid memory cube (HMC) with a stack of memory die connected by through-silicon vias (TSVs) and a high-speed logic layer, which allows for a flexible memory system with a low contact count and low power profile by tying vaults together, enabling efficient data transfer and minimizing the footprint on the controller.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a stack of memory die with high signal count and high bandwidth is implemented, then memory bandwidth and efficiency are improved, but host interface cost and complexity increase

Engineering Contradiction:
Improvememory bandwidthVSAvoidhost interface complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The memory system is divided into multiple independent memory die stacked vertically, with each die handling a portion of the total bandwidth. This segmentation allows the high bandwidth to be achieved through parallel operation of multiple smaller units rather than requiring a single complex high-bandwidth interface

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from a planar memory architecture to a three-dimensional stacked architecture using through-silicon vias (TSVs). This vertical stacking enables multiple memory die to be connected in the vertical dimension, multiplying the bandwidth capability without increasing the horizontal footprint or interface complexity at any single level

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If memory is placed on the same substrate as controller, then memory bandwidth and coupling to processor are improved, but manufacturing complexity increases

Engineering Contradiction:
Improvememory bandwidthVSAvoidmanufacturing complexity
Core Design Contradiction:
ProductivityVSEase of manufacture

Solution Approach 1:

The integrated memory controller system is segmented into separate functional blocks on the substrate, with standardized interfaces between components. This modular segmentation allows each component to be manufactured and tested independently before final assembly, reducing overall manufacturing complexity while maintaining the benefits of tight coupling

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The controller substrate is designed with universal, standardized interfaces and mounting structures that can accommodate different memory die configurations. This universality allows the same substrate design to be used across multiple product variants, simplifying the manufacturing process while enabling flexible memory bandwidth scaling

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11769534B2Flexible memory system with a controller and a stack of memory
Publication Date: 2023.09.26 MICRON TECHNOLOGY INC
  • US11769534B2 patent drawing
  • US11769534B2 patent drawing
  • US11769534B2 patent drawing

AI summary

Embodiments of a system and method for providing a flexible memory system are generally described herein. In some embodiments, a substrate is provided, wherein a stack of memory is coupled to the substrate. The stack of memory includes a number of vaults. A controller is also coupled to the substrate and includes a number of vault interface blocks coupled to the number of vaults of the stack of memory, wherein the number of vault interface blocks is less than the number of vaults.