Stacked Non-Volatile Memory Layout With Vertical Passive Elements
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Solution Overview
Problem
Existing three-dimensional non-volatile memory devices face challenges in increasing capacity while minimizing chip size, particularly in the passive element components of the peripheral circuit region.
Innovation Solution
The implementation of a non-volatile memory device with a chip-to-chip structure, where a second chip is stacked on a first chip, incorporating dummy pads and contact plugs that form vertical capacitors or resistors, allowing for high-capacity passive elements without increasing chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of word lines stacked on the substrate is increased to increase memory capacity, then the capacity of passive elements in the peripheral circuit region should be increased, but the chip size increases
Solution Approach 1:
The patent transitions from planar passive elements to vertical three-dimensional passive elements by stacking electrode patterns and insulating layers vertically. The electrode patterns extend in the third direction (vertical direction) perpendicular to the substrate, enabling high-capacity passive elements without increasing the chip's planar area.
Solution Approach 2:
The patent embeds multiple layers of electrode patterns and insulating layers within each other in the vertical direction. The first electrode pattern is nested with the second electrode pattern, which is nested with the third electrode pattern, creating a compact vertical structure that maximizes passive element capacity within the available vertical space.
2Quantity of substance
If vertical capacitors or resistors are integrated using dummy pads and contact plugs, then passive element capacity is enhanced, but device structure becomes more complex
Solution Approach 1:
The patent makes the dummy pads and contact plugs serve dual functions: they act as structural components for chip-to-chip bonding while simultaneously forming vertical passive elements (capacitors or resistors) when connected to electrode patterns. This multi-functionality reduces the need for separate dedicated passive element structures.
Solution Approach 2:
The patent combines the bonding pad structure with the passive element structure. The dummy pads and contact plugs that would otherwise be unused are merged with the electrode patterns to form functional passive elements, eliminating the need for separate bonding pads and reducing overall device complexity.
Data Source
AI summary
A non-volatile memory device includes a first chip including a first substrate and a circuit element, and a second chip stacked on the first chip. The second chip includes a second substrate including a first cell region and a second cell region, gate electrodes stacked on the second cell region of the second substrate, wherein the gate electrodes are between the second substrate and the first chip, an upper insulating layer configured to cover the second substrate, dummy pads and input/output pads on the upper insulating layer, a cover layer on the upper insulating layer to cover the dummy pads, wherein the cover layer is configured to expose the input/output pads to an outside, and dummy contact plugs on one side of the second substrate, wherein the dummy contact plugs are configured to penetrate the upper insulating layer and electrically connect the dummy pads and the circuit element.