Stacked Memory Cell Wiring Layout for Lower Via Height
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Solution Overview
Problem
Existing semiconductor devices face manufacturing difficulties due to complex layer configurations and high aspect ratios in memory cell layers, leading to reduced yield and increased manufacturing costs.
Innovation Solution
A semiconductor device with a first and second memory cell layer, each with specific selection lines and memory cells, and a wiring layer between them, configured using a dual damascene process to simplify the layer structure and reduce manufacturing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple storage layers are integrated in a single memory cell layer, then storage capacity is improved, but manufacturing complexity increases and yield decreases
Solution Approach 1:
The patent divides the memory structure into separate first and second memory cell layers, each containing a specific number of storage layers. This segmentation allows each layer to be manufactured with controlled complexity while achieving high total storage capacity through vertical stacking of multiple manageable layers.
2Quantity of substance
If the number of layers in each memory cell layer is increased, then storage capacity is improved, but via height increases and manufacturing difficulty increases
Solution Approach 1:
By distributing storage layers across multiple separate memory cell layers rather than concentrating them in one layer, the patent reduces the number of vias and their heights within each individual layer, improving manufacturing precision while maintaining total storage capacity.
Solution Approach 2:
The patent transitions from a planar arrangement of storage layers to a three-dimensional stacked configuration with multiple memory cell layers arranged vertically. This dimensional change allows storage capacity to increase without proportionally increasing via height within each layer, as vias can be distributed across multiple shorter vertical segments.
3Reliability
If wiring and vias use different materials, then electrical performance is improved, but manufacturing steps increase and costs increase
Solution Approach 1:
The patent merges the material systems for wiring and vias by using the same conductive material for both inter-layer vias and in-layer word/bit lines. This consolidation reduces the number of distinct manufacturing processes required while maintaining acceptable electrical performance through optimized material selection and geometry.
Data Source
AI summary
A semiconductor device according to an embodiment of the present disclosure includes: a first memory cell layer including a first selection line extending in a first direction, a second selection line extending in a second direction, and a first memory cell coupled to the first selection line and the second selection line, a second memory cell layer provided above the first memory cell layer, and including a third selection line extending in the first direction, a fourth selection line extending in the second direction, and a second memory cell coupled to the third selection line and the fourth selection line; and a first wiring layer provided between the first memory cell layer and the second memory cell layer and including a first metal wiring line.