3D Memory Stack Layout for Density and High-Voltage Integration
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Solution Overview
Problem
The challenge lies in scaling down planar memory devices due to limitations in feature size and increasing costs, as well as the difficulty in integrating 3D NAND Flash memory devices with expanding peripheral circuits, which require higher voltages and result in increased chip size and complexity.
Innovation Solution
The integration of 3D memory devices with 3D DFM and NAND memory cell arrays, where peripheral circuits are stacked in different planes with varying voltages, allowing for reduced chip size and improved performance by using hybrid bonding and transfer bonding techniques, and employing capacitor-free multi-gate vertical 1T memory structures for enhanced data retention and reduced leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes by improving process technology, then memory density is improved, but feature sizes approach a lower limit making planar process challenging and costly
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional stacked architecture. Multiple semiconductor structures are vertically stacked to form memory cells in the third dimension, allowing continued density improvement without further reducing lateral feature sizes. This dimensional transition resolves the contradiction by providing a new scaling pathway that avoids the manufacturing precision limits of planar scaling.
2Adaptability or versatility
If 3D NAND Flash memory devices are integrated with expanding peripheral circuits, then functionality is improved, but chip size and complexity increase
Solution Approach 1:
The patent merges memory cell arrays and peripheral circuits into a single integrated 3D semiconductor structure. Both components are formed within the same stacked architecture, sharing common substrates, interconnect layers, and fabrication processes. This integration eliminates the need for separate chips or complex inter-chip connections, reducing overall chip size and complexity while maintaining full functionality.
Solution Approach 2:
The stacked semiconductor structure serves multiple functions simultaneously: different levels contain memory cell arrays for data storage, while other levels contain peripheral circuits for data processing and control. The same physical structure supports both storage and computational functions, enabling the device to adapt to various operational requirements without increasing chip size.
3Adaptability or versatility
If peripheral circuits requiring higher voltages are integrated with 3D NAND Flash memory, then operational capability is improved, but voltage management complexity increases
Solution Approach 1:
The patent implements local quality by providing different voltage levels to different regions of the stacked structure. Peripheral circuits requiring higher voltages are located in specific semiconductor levels with dedicated voltage supply paths, while memory cell arrays operate at standard voltages. This spatial differentiation of voltage requirements allows high-voltage operational capability while managing voltage complexity through localized power delivery rather than system-wide voltage management.
Data Source
AI summary
Three-dimensional (3D) memory devices and fabricating methods are disclose. A disclosed 3D memory device can comprises, a first semiconductor structure comprising an array of first type memory cells, a second semiconductor structure comprising an array of second type memory cells different from the first type memory cells, a third semiconductor structure comprising a first peripheral circuit, and a fourth semiconductor structure comprising a second peripheral circuit. The third semiconductor structure is sandwiched between the first semiconductor structure and the fourth semiconductor structure, and the fourth semiconductor is sandwiched between the second semiconductor structure and the third semiconductor structure.