Stacked Semiconductor Memory Voltage Signal Noise Reduction
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Solution Overview
Problem
Conventional semiconductor memory devices suffer from noise in voltage signals due to long and resistive wiring paths from the I/O region to the memory cell regions, which degrades the performance of the memory system.
Innovation Solution
The solution involves a semiconductor memory device architecture where the input/output circuit and memory cell regions are implemented as separate chips, with power supply and ground voltage signals being routed through separate paths outside the input/output circuit, using conductive means such as vias to directly supply voltage to the memory cells, thereby reducing noise interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If voltage signals are supplied through the I/O region to the cell regions, then the memory device can operate with integrated input/output and storage functions, but the long and resistive wiring paths generate noise that degrades signal quality
Solution Approach 1:
The patent divides the semiconductor chip into separate functional regions: an I/O region for input/output operations and cell regions for memory storage. By spatially segmenting these functions and providing dedicated voltage supply paths to each, the patent reduces the length of wiring paths and minimizes noise generation while maintaining integrated functionality.
Solution Approach 2:
The patent introduces intermediate voltage supply structures (such as voltage supply lines and wiring paths) that act as mediators between the power source and the memory cells. These intermediary structures are specifically designed to reduce resistance and minimize noise, thereby improving signal quality without compromising the integrated architecture.
2Ease of manufacture
If aluminum wiring is used to supply voltage signals from the I/O region to the cell regions, then the device can be manufactured with standard materials and processes, but the relatively large resistance of the wiring paths generates noise
Solution Approach 1:
The patent modifies the electrical parameters of the wiring paths by optimizing their dimensions, materials, and configurations. Specifically, the patent adjusts the wiring path geometry and employs materials with reduced resistance characteristics, thereby decreasing the resistive effects and associated noise while remaining compatible with standard manufacturing processes.
3Ease of operation
If the I/O region is positioned in the central region of the semiconductor chip, then the input/output circuit can be centrally located for balanced signal distribution, but the paths of power supply voltage and ground voltage become relatively long
Solution Approach 1:
The patent addresses the path length issue by utilizing three-dimensional wiring structures and vertical interconnects in addition to horizontal routing. By employing vias and multi-layer interconnect architectures, the patent reduces the effective length of voltage supply paths while maintaining the central location of the I/O region for balanced signal distribution.
Data Source
AI summary
Provided are a semiconductor memory device and a method of driving the device which can improve a noise characteristic of a voltage signal supplied to a memory cell of the device. The semiconductor memory device includes a first semiconductor chip and one or more second semiconductor chips stacked on the first chip. The first chip includes an input/output circuit for sending/receiving a voltage signal, a data signal, and a control signal to/from an outside system. The one or more second semiconductor chips each include a memory cell region for storing data. The second semiconductor chips receive at least one signal through one or more signal paths that are formed outside the input/output circuit of the first chip.