Stacked Semiconductor Memory Layout for Stable Internal Voltage
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Solution Overview
Problem
Existing semiconductor memory devices face issues with unstable internal voltage supply to peripheral circuits due to high power consumption, leading to transient voltage dips and reduced operational reliability and performance.
Innovation Solution
The semiconductor memory device is designed with a CoP (core-peripheral) structure where the voltage generator is positioned close to the peripheral circuits, reducing the supply path length and ensuring stable internal voltage delivery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the voltage generator is positioned far from the peripheral circuits, then the device area is reduced, but the internal voltage supply becomes unstable due to high power consumption
Solution Approach 1:
The patent transitions from a planar layout to a three-dimensional stacked architecture, placing the voltage generator in a lower semiconductor substrate beneath the memory cell array. This vertical arrangement reduces the supply path length and improves voltage stability without increasing the planar device area, effectively resolving the contradiction between area minimization and voltage supply reliability.
2Reliability
If the supply path length is reduced, then the internal voltage supply stability is improved, but the device complexity increases
Solution Approach 1:
The patent merges the voltage generator and peripheral circuits into a single lower semiconductor substrate, which is then bonded to the upper substrate containing the memory cell array. This integration reduces the overall supply path length and improves voltage stability while managing structural complexity through systematic design of the stacked configuration and inter-substrate bonding interfaces.
3Productivity
If the voltage generator is integrated closer to the peripheral circuits, then the operational performance is improved, but the manufacturing process complexity increases
Solution Approach 1:
The patent divides the semiconductor device into two separate substrates: an upper substrate for the memory cell array and a lower substrate for the voltage generator and peripheral circuits. This segmentation allows each substrate to be manufactured and optimized independently, then bonded together, thereby improving operational performance through closer integration while managing manufacturing complexity through modular fabrication processes.
Data Source
AI summary
Disclosed is a semiconductor memory device which includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a memory cell array, which is formed in a memory area and includes bit lines and word lines, and a plurality of upper metal pads. The second semiconductor structure is disposed below the first semiconductor structure and includes a plurality of lower metal pads respectively bonded to the plurality of upper metal pads, peripheral circuits disposed under the memory area, and a voltage generator disposed below the memory area and providing an internal voltage to one or more of the peripheral circuits. The upper metal pads are electrically connected to the bit lines or the word lines, and the lower metal pads are electrically connected to terminals of the peripheral circuits.