Stacked Semiconductor Memory Layout for Lower-Cost Wafer Assembly

Solution Overview

Problem

The existing methods for manufacturing stacked semiconductors, such as those described in Japanese Unexamined Patent Application (Translation of PCT Application), Publication No. 2013-524519, result in increased assembly time and high manufacturing costs due to the complex stacking process of multiple die stacks on an interface die.

Innovation Solution

A stacked semiconductor design that includes a logic chip and a memory unit with multiple memory chips, each having memory bodies with memory circuits arranged in parallel and connected by a connecting portion. This design allows for efficient stacking and alignment of memory and logic chips, reducing the need for complex assembly processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multiple die stacks are stacked on an interface die with positioning, then a large-capacity memory can be realized, but assembly time is increased and manufacturing costs are high

Engineering Contradiction:

Improvememory capacityVSAvoidassembly time

Core Design Contradiction:

Quantity of substanceVSLoss of time

Solution Approach 1:

The patent merges multiple memory die stacks onto a single substrate without requiring an interface die for positioning. This consolidation approach combines the functions of multiple components into one integrated structure, eliminating the need for complex stacking and positioning operations, thereby reducing assembly time while maintaining large memory capacity.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent transitions from a three-dimensional stacking approach (multiple die stacks on interface die) to a planar arrangement on a single substrate. This dimensional change from vertical stacking to horizontal integration simplifies the assembly process and reduces manufacturing complexity while achieving the same memory capacity goal.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If multiple die stacks are stacked on an interface die with positioning, then a large-capacity memory can be realized, but manufacturing costs are high

Engineering Contradiction:

Improvememory capacityVSAvoidmanufacturing cost

Core Design Contradiction:

Quantity of substanceVSEase of manufacture

Solution Approach 1:

The patent merges multiple memory die stacks onto a single substrate without requiring an interface die for positioning. This consolidation approach combines the functions of multiple components into one integrated structure, eliminating the need for complex stacking and positioning operations, thereby reducing assembly time while maintaining large memory capacity.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent transitions from a three-dimensional stacking approach (multiple die stacks on interface die) to a planar arrangement on a single substrate. This dimensional change from vertical stacking to horizontal integration simplifies the assembly process and reduces manufacturing complexity while achieving the same memory capacity goal.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Ease of manufacture

If memory bodies are provided in parallel with connecting portions, then assembly process is simplified and manufacturing cost is reduced, but device complexity increases

Engineering Contradiction:

Improveassembly processVSAvoidmemory chip structure

Core Design Contradiction:

Ease of manufactureVSDevice complexity

Solution Approach 1:

The patent segments the memory chip into multiple memory bodies arranged in parallel, each connected through connecting portions. This segmentation allows for modular assembly and simplified manufacturing processes while distributing the complexity across multiple independent units rather than one complex integrated structure.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The connecting portions serve multiple functions: they connect memory bodies in parallel, provide signal routing, and enable modular assembly. This multi-functionality reduces the need for separate components and simplifies the overall assembly process while managing device complexity through integrated design.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS12334473B2Stacked semiconductor, wafer stack, method of manufacturing stacked semiconductor, assistance device, and program

Publication Date: 2025.06.17 ULSTREETCAREMORY INC

AI summary

A laminated semiconductor which enables curbing of manufacturing cost; a wafer laminate; a method for manufacturing the laminated semiconductor; an assistance device; and a program. This laminated semiconductor formed by laminating a plurality of chips is provided with a logic chip; and a memory part that is stacked on the logic chip and has at least one memory chip communicable with the logic chip. The memory chip has at least two memory bodies that have memory circuits and that are arranged side by side in a direction intersecting the stacking direction; and a connection part which is provided with a prescribed width between the memory bodies and which connects the memory bodies arranged side by side.