Stacked Memory Substrate Structure for Warpage Control
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Solution Overview
Problem
Three-dimensional stacked semiconductor storage devices face increased warpage issues during stacking, leading to package defects, which are difficult to address solely by forming patterns on wiring layers or passivation films due to differing warped states between semiconductor chips.
Innovation Solution
Incorporating a layer with a Young's modulus higher than silicon and/or internal stress greater than silicon oxide within the substrate to act as a support layer, reducing warpage by controlling deformation and thermal expansion coefficients, and using materials like silicon nitride, metal oxides, or metal nitrides to achieve the necessary properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a layer with high Young's modulus and internal stress is embedded in the substrate, then warpage and deformation are reduced, but device complexity increases
Solution Approach 1:
The patent embeds a functional layer within the substrate structure, creating a nested configuration where the high-stiffness layer (silicon nitride, metal oxide, or metal nitride) is integrated inside the semiconductor substrate. This nesting approach provides warpage control functionality while maintaining a compact overall structure.
Solution Approach 2:
The patent employs composite material construction by combining the semiconductor substrate with an embedded layer of silicon nitride, metal oxide, or metal nitride. This composite structure leverages the high Young's modulus and internal stress properties of the embedded layer to counteract warpage while preserving the electrical functionality of the semiconductor substrate.
2Quantity of substance
If multiple semiconductor chips are stacked three-dimensionally, then storage capacity increases, but warpage and package defects increase
Solution Approach 1:
The embedded layer acts as a counterweight structure within the substrate, generating internal stress that opposes and balances the warpage forces arising from thermal expansion mismatches and mechanical stresses during three-dimensional stacking. This internal counterbalancing mechanism prevents convex or concave deformation of the stacked chips.
Solution Approach 2:
The patent modifies the mechanical parameters of the substrate by embedding a layer with specifically controlled Young's modulus (higher than silicon) and internal stress (higher than silicon oxide). This parameter adjustment enables the substrate to maintain dimensional stability under the thermal and mechanical loads experienced during multi-chip stacking.
3Manufacturing precision
If patterns are formed on wiring layers or passivation films to address warpage, then manufacturing process complexity increases, but effectiveness is limited due to differing warped states
Solution Approach 1:
The patent implements warpage control measures during the substrate fabrication stage by embedding the high-stiffness layer, rather than attempting to correct warpage after chip fabrication through pattern formation on wiring layers. This preliminary action addresses the root cause of warpage before the chips are assembled, making the process more effective and efficient.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces warpage and deformation in semiconductor devices, enhancing manufacturing reliability by preventing convex or concave warping and maintaining mechanical strength, while minimizing electrical interference.
Implementation Method 1
The layer has a Young's modulus that is higher than that of silicon and/or an internal stress that is higher than that of silicon oxide
Implementation Method 2
The layer has a Young's modulus that is higher than that of silicon and/or an internal stress that is higher than that of silicon oxide
Implementation Method 3
reducing warpage by controlling deformation and thermal expansion coefficients
Data Source
AI summary
According to one embodiment, a semiconductor device includes a first substrate, a second substrate joined to the first substrate. A first region of the semiconductor device that includes a peripheral circuit is between the first substrate and the second substrate. A second region that includes a memory cell array is between the first region and the second substrate. A layer that is embedded in the second substrate has a Young's modulus that is higher than that of silicon and/or an internal stress that is higher than that of silicon oxide.