3D Stacked Memory Package Layout for Warpage-Stable Interconnects
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in achieving high functionality, miniaturization, and high-speed performance, particularly in three-dimensional stacked memory modules, where there is a need for efficient electrical connectivity and structural stability to prevent warpage and ensure reliable signal transmission.
Innovation Solution
A semiconductor package design featuring a first and second redistribution layer with insulating and conductive patterns, a stacked memory module, a semiconductor chip, and a dummy structure to provide electrical connectivity and structural support, along with bumps and vias for signal transmission, and a mold layer for protection and alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If three-dimensional stacking is used to increase functionality, then device capability is improved, but structural stability deteriorates due to warpage
Solution Approach 1:
The dummy structure is configured to have substantially the same height as the stacked memory module, creating a homogeneous top surface. This height matching ensures uniform stress distribution across the package substrate, preventing warpage while maintaining the three-dimensional stacked configuration for enhanced functionality.
Solution Approach 2:
The dummy structure acts as a mediator between the stacked memory module and the package substrate. It provides mechanical support and stress compensation to the stacked memory module, ensuring structural stability without interfering with the electrical connectivity or functionality of the memory devices.
2Adaptability or versatility
If three-dimensional stacking is used to increase functionality, then device capability is improved, but manufacturing complexity worsens
Solution Approach 1:
The dummy structure is formed on the package substrate before the stacked memory module is mounted. This preliminary formation simplifies the overall manufacturing process by pre-establishing the structural support framework, reducing the complexity of subsequent assembly steps while enabling three-dimensional stacking for enhanced functionality.
3Volume of moving object
If miniaturization is pursued, then device size is reduced, but electrical connectivity deteriorates
Solution Approach 1:
The patent transitions from two-dimensional planar interconnection to three-dimensional vertical stacking with redistribution layers. This dimensional change allows electrical signals to be routed vertically through multiple layers via vias and conductive patterns, maintaining reliable electrical connectivity while reducing the footprint and enabling miniaturization of the device.
Data Source
AI summary
A semiconductor package includes: a first redistribution layer including a first insulating layer and a first conductive pattern disposed in the first insulating layer; a first connection terminal disposed on a first surface of the first redistribution layer; a stacked memory module disposed on second surface of the first redistribution layer; a second redistribution layer disposed on the stacked memory module, and including a second insulating layer and a second conductive pattern disposed in the second insulating layer; a first bump disposed on a first surface of the second redistribution layer, and in contact with the stacked memory module; a first semiconductor chip disposed on second surface of the second redistribution layer; and a dummy structure disposed between the first redistribution layer and the second redistribution layer and spaced apart from the stacked memory module.