Stacked Memory Die Layout With Wireless Logic Communication
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Solution Overview
Problem
Existing semiconductor structures face challenges in increasing the number of stacked memory die layers without compromising performance, particularly due to communication delays and process complexity in wired connections.
Innovation Solution
A semiconductor structure design with parallel stacking of memory dies and wireless communication components, utilizing adhesive films for adhesion and power supply wiring layers extending along the active surface of memory dies, simplifying the manufacturing process and reducing communication delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacked layers of memory dies is increased, then the capacity density is improved, but the communication delay increases and performance deteriorates
Solution Approach 1:
The patent transitions from traditional vertical stacking (perpendicular to logic die) to parallel stacking (parallel to logic die upper surface). This dimensional change allows memory dies to be arranged in a plane rather than stacked vertically, increasing the number of memory dies that can be integrated without increasing the vertical distance for signal transmission, thus reducing communication delay while improving capacity density.
Solution Approach 2:
The patent divides the memory structure into multiple memory components, where each memory component contains multiple memory dies arranged in parallel. This segmentation allows for better organization and reduces the communication distance between memory dies and the logic die, thereby reducing communication delay while maintaining high capacity density.
2Quantity of substance
If the number of stacked layers of memory dies is increased, then the capacity density is improved, but the manufacturing complexity increases
Solution Approach 1:
By changing from vertical to parallel stacking, the patent simplifies the manufacturing process. Parallel stacking eliminates the need for complex through-silicon via (TSV) structures and reduces the number of bonding interfaces required, thereby reducing manufacturing complexity while enabling higher capacity density.
Solution Approach 2:
The patent introduces a support structure as an intermediary element that holds multiple memory components in parallel arrangement. This support structure simplifies the manufacturing process by providing a stable platform for mounting memory dies, reducing the complexity of aligning and bonding multiple memory layers directly to the logic die.
3Device complexity
If traditional vertical stacking is used, then the structure is simple, but the communication delay increases and performance decreases
Solution Approach 1:
The patent maintains structural simplicity by using a parallel arrangement that is easier to manufacture than vertical stacking, while simultaneously reducing communication delay. The parallel configuration shortens the signal transmission path between memory dies and the logic die, improving performance without significantly increasing structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design allows for increased capacity density and improved communication speed by minimizing communication distance and process complexity, while maintaining structural strength and reducing electromagnetic interference.
Implementation Method 1
a first adhesive film arranged between any two adjacent memory components of the plurality of memory components and adhered to the any two adjacent memory components
Data Source
AI summary
A semiconductor structure, a method for manufacturing a semiconductor structure and a semiconductor device are provided. The semiconductor structure comprises: a logic die provided with a first wireless communication component; a plurality of memory components arrayed in a first direction and stacked on an upper surface of the logic die, the first direction being parallel to the upper surface of the logic die; and a first adhesive film arranged between any two adjacent memory components of the plurality of memory components and adhered to the any two adjacent memory components. Each of the plurality of memory components includes a plurality of memory dies arrayed in the first direction. Each of the plurality of memory dies is provided with a second wireless communication component. The second wireless communication component is in wireless communication with the first wireless communication component.