Stacked Memory Chip Wiring Layout for Uniform Signal Delays
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor devices face challenges in maintaining high waveform quality for signals transmitted between semiconductor controller chips and memory chips due to variations in signal transmission characteristics.
Innovation Solution
The semiconductor device employs a configuration where multiple semiconductor memory chips are stacked with offset positions, and wires connecting these chips to the controller chip are designed to have consistent signal transmission characteristics, minimizing signal degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple semiconductor memory chips are stacked with offset positions to reduce signal quality deterioration, then signal transmission characteristics become more consistent, but device complexity increases due to the need for precise positioning and wiring
Solution Approach 1:
The patent applies asymmetry by intentionally offsetting the positions of semiconductor memory chips in the stack rather than aligning them symmetrically. This asymmetric arrangement allows wires to connect to electrode pads at optimized positions, reducing signal transmission delay variations and improving signal quality while managing the inherent complexity through deliberate geometric configuration
Solution Approach 2:
The patent changes the positional parameters of chips in the stack, specifically setting offset distances (e.g., first offset distance D1, second offset distance D2) to optimize wire lengths and signal transmission characteristics. By adjusting these geometric parameters, the patent achieves more consistent signal delays across different chip connections, thereby improving reliability
2Reliability
If wires are designed to have consistent signal transmission characteristics, then waveform quality improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs preliminary action by pre-planning and pre-designing the wire routing paths and connection points before manufacturing. The wire connections are designed to connect to specific electrode pads (e.g., ninth electrode pad 9, eleventh electrode pad 11, thirteenth electrode pad 13, fifteenth electrode pad 15) at predetermined locations, ensuring consistent transmission characteristics are built into the structure before fabrication, thus reducing the actual manufacturing precision burden
Solution Approach 2:
The patent achieves equipotentiality in terms of signal transmission by designing wire paths that result in substantially equal transmission delays from the controller chip to each memory chip. This is accomplished by carefully balancing wire lengths and connection points so that signals arrive at comparable times, improving waveform quality while managing manufacturing precision through symmetric delay compensation
Data Source
AI summary
According to one embodiment, a semiconductor device includes a substrate, a chip stack with a plurality of first semiconductor chips, a first wire group, a second wire, and a third wire. The substrate has a first surface with a first pad and a second pad. Each first semiconductor chip has a surface facing away from the first surface with a third pad and a fourth pad. The first wire group includes a plurality of first wires that each electrically connect the first pad to a third pad one of the first semiconductor chips. The second wire electrically connects the second pad to the fourth pad of the first semiconductor chip in the chip stack closest to the substrate. The third wire electrically connects the fourth pads of each of first semiconductor chips.