Stacked Memory Cell Wiring Isolation for Faster Semiconductor Operation
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Solution Overview
Problem
In semiconductor devices with stacked OS and Si transistors, long wirings for connecting circuits increase parasitic capacitance and resistance, leading to decreased operating speed and reliability.
Innovation Solution
A semiconductor device configuration with overlapping element layers, utilizing OS transistors and Si transistors, includes switch circuits to establish non-conduction states between wirings, reducing power consumption and enhancing operating speed and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacks of element layers including OS transistors is increased to achieve higher integration, then memory density is improved, but wiring length increases leading to increased parasitic capacitance and resistance
Solution Approach 1:
The patent introduces switch circuits that segment the electrical connection paths between element layers. By controlling the switch circuits, data signals can be selectively connected to specific element layers, preventing signals from traveling through unnecessary intermediate layers and reducing parasitic capacitance and resistance in the wiring paths.
Solution Approach 2:
The switch circuits act as intermediaries between the bit line driver circuit and the memory cells in different element layers. These intermediaries control the electrical connectivity, allowing data to be efficiently transferred only to the target layer while isolating other layers, thereby reducing the effective wiring length and parasitic effects.
2Productivity
If wiring length is increased to connect bit line driver circuit to memory cells in upper element layers, then integration is improved, but parasitic capacitance and resistance increase
Solution Approach 1:
The patent employs dynamic control of switch circuits to adjust electrical connectivity based on operational requirements. During data write or read operations, the switch circuits dynamically establish non-conduction states in specific paths, optimizing the electrical connection for the current operation and minimizing parasitic effects on active data paths.
Solution Approach 2:
The switch circuits extract and isolate unnecessary electrical connection paths between element layers. By establishing non-conduction states in paths that do not require data transfer, the patent removes irrelevant wiring segments from the active signal path, thereby reducing parasitic capacitance and resistance that would otherwise affect data reliability.
3Loss of energy
If switch circuits are added to establish non-conduction states between wirings, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The switch circuits are integrated into the existing element layer structure and serve multiple functions: controlling data transfer paths, reducing power consumption by isolating inactive layers, and maintaining signal integrity. This multi-functionality reduces the need for separate dedicated components, thereby limiting the increase in overall device complexity.
Solution Approach 2:
The switch circuits are merged with the bit line driver circuit and memory cell structures within the same element layers. By combining the switching function with the existing circuit architecture, the patent minimizes additional complexity while achieving power reduction through selective activation of data paths.
Data Source
AI summary
A semiconductor device with a novel configuration is provided. The semiconductor device includes a first element layer including a bit line driver circuit; a second element layer including a first switch circuit, a first memory cell, and a first wiring provided between the first switch circuit and the first memory cell; and a third element layer including a second switch circuit, a second memory cell, and a second wiring provided between the second switch circuit and the second memory cell. The first switch circuit has a function of establishing a non-conduction state between the first wiring and a third wiring in data write operation or read operation of the second memory cell. The second switch circuit has a function of establishing a non-conduction state between the second wiring and the third wiring in data write operation or read operation of the first memory cell.