Stacked Memory Chip Address Control via XOR Selection Signals
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Solution Overview
Problem
Existing memory devices with stacked memory chips face challenges in efficiently controlling the switching between active and inactive modes when operating as single or stacked memory devices, requiring precise management of address pads and selection signals to ensure proper operation.
Innovation Solution
The solution involves setting internal address counter codes for each memory chip based on an input address code and selection signal, using logical exclusive OR operations to determine the most significant bit, allowing each chip to alternate between active and inactive modes effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory chips are stacked to increase storage capacity, then the quantity of memory chips increases, but the complexity of controlling switching between active and inactive modes increases
Solution Approach 1:
The patent divides the control mechanism into segments by providing separate selection signals (first selection signal for top chip, second selection signal for bottom chip) and separate internal address counter codes for each memory chip. This segmentation allows independent control of each chip's active/inactive state, resolving the complexity issue while maintaining the ability to stack multiple chips
Solution Approach 2:
The patent applies preliminary action by pre-setting the most significant bit of internal address counter codes through XOR operations with selection signals before access operations begin. This preliminary configuration enables automatic mode switching without requiring complex real-time control logic during operation
2Device complexity
If address pads are reused for stacked memory chips, then the number of address pads is reduced, but the precision of address identification decreases
Solution Approach 1:
The patent applies local quality by configuring different initial values for the most significant bit of internal address counter codes in different memory chips through XOR operations with their respective selection signals. This creates distinct address identification characteristics for each chip location, enabling precise address identification even when physical address pads are shared
Solution Approach 2:
The patent changes the parameter of internal address counter code initial values based on selection signals and chip positions. By XORing the most significant bit with selection signal values, the system dynamically adjusts address parameters to maintain precise identification across stacked chips while reusing physical address pads
3Adaptability or versatility
If memory chips switch between active and inactive modes, then the operational flexibility increases, but the switching control difficulty increases
Solution Approach 1:
The patent implements self-service by enabling memory chips to automatically determine their active or inactive state through internal address counter code comparisons. Each chip independently evaluates its internal counter against the input address code, eliminating the need for external switching control logic and simplifying operation while maintaining flexible mode switching
Data Source
AI summary
A memory device is provided. The memory device comprises a plurality of memory chips. The plurality of memory chips receive an input address code and alternately operate in an active mode. Each memory chip receives a selection signal and operates according to an internal address counter code. For each memory chip, the respective internal address counter code is initially set according to the input address code and the respective selection signal.