Stacked MEMS and ASIC Semiconductor Package Design
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Solution Overview
Problem
There is a continuous demand for smaller semiconductor packages at reduced costs, as existing methods like chip scale and wafer level packaging, and system-in-packages, face challenges in minimizing size and cost, particularly due to the expensive processing required for conductive through vias.
Innovation Solution
The solution involves stacking a smaller MEMS die on a larger ASIC die, electrically coupling them with conductive wires, and using a molding compound to encapsulate the wires and conductive bumps, thereby eliminating the need for through vias and minimizing package height and size, while maintaining mechanical support and protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conductive through vias are used to couple MEMS and ASIC dice together, then package size is reduced, but manufacturing cost increases
Solution Approach 1:
The patent extracts and eliminates the expensive through via processing step from the manufacturing sequence. Instead of forming conductive vias through the die stack, the invention uses wire bonding to achieve electrical coupling, thereby removing the costly via formation process while maintaining electrical connectivity between MEMS and ASIC dice.
Solution Approach 2:
The patent replaces expensive, complex through via structures with simpler, cheaper wire bonds and surface-mounted conductive elements. The wire bonds serve as temporary-looking but functional electrical pathways that achieve the same coupling purpose at significantly reduced manufacturing cost.
2Area of stationary object
If the smaller die is stacked on the larger die, then package footprint is reduced, but package height may increase
Solution Approach 1:
The patent transitions from planar side-by-side die arrangement to vertical stacking configuration. By moving the smaller die to the third dimension (stacking it on top of the larger die), the footprint is dramatically reduced while the height increase is managed through optimized wire bond lengths and compact packaging.
Solution Approach 2:
The patent implements a nested die configuration where the smaller die is positioned on top of the larger die, creating a vertically integrated structure. This nesting approach maximizes space utilization by stacking functional blocks vertically rather than arranging them horizontally.
3Ease of manufacture
If conductive wires are used to electrically couple stacked dice, then manufacturing cost is reduced, but electrical connection reliability may be affected
Solution Approach 1:
The patent performs wire bonding and electrical coupling operations before final die stacking and encapsulation. By establishing electrical connections in advance, the system ensures reliable bonding interfaces are created under controlled conditions, and subsequent packaging steps protect these connections rather than exposing them to stress.
Solution Approach 2:
The patent applies molding compound encapsulation that provides mechanical protection and stress relief to the wire bonds and conductive elements. This cushioning effect protects the delicate electrical connections from mechanical stress, thermal expansion, and environmental damage, thereby enhancing long-term reliability.
Data Source
AI summary
One or more embodiments of the present disclosure are directed to packages that include a stacked microelectromechanical sensor MEMS die and an application-specific integrated circuit (ASIC) die. The smaller of the MEMS die and the ASIC die is stacked on the larger of the MEMS die and the ASIC die. The larger of the two dice may form one or more dimensions of the package. In one embodiment, a bottom surface of the larger of the two dice forms an outer surface of the package. In that regard, the package may take less lateral space on another component, such as a board or other package.