Vertically Stacked MEMS-CMOS-MEMS Platform for Stress Isolation
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Solution Overview
Problem
Existing MEMS devices face challenges in combining multiple MEMS substrates with CMOS substrates in a single package, requiring different environments and stress isolation to optimize performance, while minimizing package size and addressing stress/strain issues.
Innovation Solution
A vertically stacked package comprising a MEMS substrate, a CMOS substrate, and another MEMS substrate, connected with electrical interconnects and mechanical connections using methods like Si to SiO2 fusion bonding, eutectic bonding, or low-stress adhesive materials, with stress-relieving features such as recesses and interposers to reduce stress transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If multiple MEMS substrates are combined with CMOS substrate in a single package, then the package size is reduced and board area is minimized, but stress/strain in the substrate causes sensor performance to change
Solution Approach 1:
The package is divided into multiple separate substrates (first MEMS substrate, CMOS substrate, second MEMS substrate) stacked vertically, each maintaining its own stress characteristics while being electrically connected through interconnects. This segmentation allows each substrate to be optimized independently while achieving compact integration.
Solution Approach 2:
The CMOS substrate acts as an intermediary layer between the two MEMS substrates, providing both electrical connection and mechanical isolation. The electrical interconnects through the CMOS substrate enable signal transmission while the physical separation provides stress isolation, preventing stress transfer between the MEMS devices.
2Adaptability or versatility
If different MEMS processes are integrated in one package, then device functionality is enhanced and space is saved, but different environmental requirements cannot be met
Solution Approach 1:
Different MEMS devices are fabricated on separate substrates, allowing each substrate to be optimized for its specific environmental requirements (e.g., hermetic sealing for accelerometers, open structure for pressure sensors). The vertical stacking enables compact integration while maintaining independent environmental control for each device type.
Solution Approach 2:
Each substrate is designed with local environmental characteristics appropriate to its specific MEMS device requirements. The first MEMS substrate can be hermetically sealed for pressure-sensitive devices, while the second MEMS substrate can have open structures for ambient-sensing devices, with each substrate providing its own local environment independent of the others.
3Productivity
If substrates are mechanically connected in a stacked configuration, then integration density is increased, but stress transmission between substrates affects performance
Solution Approach 1:
The CMOS substrate serves as a stress-isolating intermediary between the two MEMS substrates. While electrical interconnects provide signal transmission through the CMOS substrate, the mechanical connection is designed to minimize stress transfer, allowing high integration density while protecting sensitive MEMS devices from stress-induced performance degradation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for efficient operation of diverse MEMS devices in a compact package, ensuring optimal performance by providing the necessary environmental conditions and stress isolation, thus reducing the impact of package stress on sensor performance.
Implementation Method 1
mechanical connections using methods like Si to SiO2 fusion bonding
Implementation Method 2
mechanical connections using methods like Si to SiO2 fusion bonding, eutectic bonding
Data Source
AI summary
A package combining a MEMS substrate, a CMOS substrate and another MEMS substrate in one package that is vertically stacked is disclosed. The package comprises a sensor chip further comprising a first MEMS substrate and a CMOS substrate with a first surface and a second surface and where the first MEMS substrate is attached to the first surface of the CMOS substrate. The package further includes a second MEMS substrate with a first surface and a second surface, where the first surface of the second MEMS substrate is attached to the second surface of the CMOS substrate and the second surface of the second MEMS substrate is attached to a packaging substrate. The first MEMS substrate, the CMOS substrate, the second MEMS substrate and the packaging substrate are provided with electrical inter-connects.