Stacked MEMS Wafer Bonding for Compact Multi-Function Integration
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Solution Overview
Problem
Existing MEMS devices face challenges in integrating multiple functionalities and reducing device size while maintaining high reliability and efficient signal transmission.
Innovation Solution
A fabrication method involving the stacking of wafers with conductive pads and electrodes, forming airtight chambers, and using eutectic bonding to connect germanium conductive pads, allowing for the integration of heterogeneous elements and amplification of signal outputs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple MEMS elements are integrated into a single chip, then device functionality and signal transmission efficiency are improved, but device complexity and fabrication difficulty increase
Solution Approach 1:
The device is divided into multiple independent wafers (first wafer, second wafer, cap wafer) that are fabricated separately and then stacked. Each wafer can be optimized independently for specific functionalities, reducing the complexity of fabricating all functions in a single chip while achieving integrated performance through the stacked architecture.
Solution Approach 2:
The patent transitions from planar integration to three-dimensional stacking by bonding multiple wafers vertically. This dimensional change allows multiple MEMS elements to be integrated along the vertical axis rather than occupying horizontal space, increasing functionality while managing complexity through spatial separation of different functional layers.
2Volume of moving object
If wafer stacking is used to integrate MEMS elements, then die size is reduced, but manufacturing precision and bonding reliability become more critical
Solution Approach 1:
Germanium conductive pads are introduced as intermediary bonding elements between the wafers. These pads facilitate precise alignment and reliable eutectic bonding during the stacking process, addressing the manufacturing precision challenges by providing a controlled interface that enhances bonding reliability while enabling compact vertical integration.
Solution Approach 2:
The patent utilizes eutectic bonding parameters (temperature, composition) to achieve reliable wafer bonding. By controlling the bonding temperature and utilizing the eutectic reaction characteristics of the germanium-containing pads, the process achieves high bonding reliability despite the increased precision requirements of wafer stacking.
3Reliability
If eutectic bonding with germanium pads is used, then bonding reliability is improved, but manufacturing process complexity increases
Solution Approach 1:
The germanium conductive pads are pre-formed on the wafers before the bonding process. This preliminary action ensures that the bonding interface is prepared in advance with the correct material composition and geometry, improving bonding reliability while allowing the actual bonding process to proceed more smoothly by eliminating the need for complex in-situ bonding procedures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the integration of diverse MEMS elements into a single chip, reducing die size and enhancing signal transmission efficiency.
Implementation Method 1
eutectically bonding the first pair structure and the second pair structure, wherein the plurality of germanium conductive pads on the third wafer are physically and electrically connected with the plurality of fourth conductive pads and the plurality of fifth conductive pads on the second wafer respectively
Implementation Method 2
welding a third wafer on the cap wafer to form a second pair structure
Data Source
AI summary
A manufacturing method for stacked microelectromechanical system (MEMS) devices is disclosed. The manufacturing method includes manufacturing a plurality of pair structures and eutectically bonding the plurality of pair structures. With the aid of the conductive pads and the conducting holes that electrically connect between the pair structures and among wafers of the pair structures, the purpose of integrating multiple wafers in a single chip and reducing a chip's size can be achieved.