Stacked MEMS Wafer Integration for High Density Sensors
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Solution Overview
Problem
Existing micromechanical sensors face challenges in achieving high integration density and robustness against substrate deformations, particularly in maintaining signal-to-noise ratio and offset stability, while also requiring efficient use of space for both MEMS functional structures and electronic evaluation circuits.
Innovation Solution
A method involving a MEMS wafer with two movable structures stacked on top of each other, where the first and second substrate layers are electrically conductively connected, and the wafer is joined with a cap wafer and an ASIC wafer using metallic bonding processes, allowing for selective electrical and mechanical connections, and utilizing SOI wafers for monocrystalline silicon material to reduce intrinsic stresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a single MEMS layer is used, then the device complexity is low, but the integration density and signal-to-noise ratio are insufficient
Solution Approach 1:
The patent transitions from a planar single-layer MEMS structure to a three-dimensional stacked configuration with multiple MEMS layers positioned at different heights. This vertical stacking enables increased integration density and capacitance per area by utilizing the third dimension, while maintaining manageable complexity through modular layer design and independent processing of each layer
2Quantity of substance
If evaluation electrodes are added in the MEMS wafer, then the capacitance per area increases, but the manufacturing complexity increases
Solution Approach 1:
The patent divides the electrode system into separate functional layers: fixed electrodes in the CMOS wafer and movable electrodes in the MEMS wafer. This segmentation allows independent optimization and processing of each electrode type, with through-silicon vias providing selective electrical connections. The segmented approach increases capacitance density while managing manufacturing complexity through specialized processing steps for each layer
3Reliability
If substrate deformations occur, then the offset stability deteriorates, but adding more evaluation electrodes can improve robustness
Solution Approach 1:
The patent combines multiple evaluation electrodes from both the CMOS wafer and MEMS wafer into a unified fully differential electrode system. This merging creates redundant measurement paths that compensate for substrate deformations, improving offset stability through differential signaling while sharing common structural elements to control complexity
4Area of stationary object
If vertical integration is implemented, then the space requirement is reduced, but the manufacturing precision requirements increase
Solution Approach 1:
The patent implements vertical integration by stacking the MEMS wafer onto the CMOS wafer in the third dimension, reducing the planar footprint while maintaining all functional elements. This approach compresses the device volume without requiring proportionally higher manufacturing precision, as each layer can be processed independently before stacking, with alignment features managing the precision requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances integration density, reduces noise, and improves offset stability by enabling fully differential capacitive electrode systems with reduced space requirements, while minimizing intrinsic stresses and crosstalk between sensor elements, effectively addressing the limitations of existing sensor technologies.
Implementation Method 1
joining the MEMS wafer to the cap wafer; joining the ASIC wafer to the joint of the MEMS wafer and the cap wafer
Data Source
AI summary
A method for manufacturing a micromechanical component, including: providing a MEMS wafer; structuring the MEMS wafer proceeding from a surface of a second substrate layer of the MEMS wafer, at least one electrically conducting connection being formed between a first substrate layer and the second substrate layer of the MEMS wafer; providing a cap wafer; joining the MEMS wafer to the cap wafer; structuring the MEMS wafer proceeding from a surface of the first substrate layer of the MEMS wafer; providing an ASIC wafer; and joining the ASIC wafer to the joint of the MEMS wafer and the cap wafer.