Stacked Micro TSV Structure for Higher Transistor Density
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Solution Overview
Problem
Current manufacturing processes for through-silicon vias (TSVs) in integrated circuits require large keep-out-regions to prevent transistor functionality breakdown due to thermo-mechanical stress, limiting transistor density and increasing the challenges of silicon substrate warpage and thermal dissipation.
Innovation Solution
The use of multi-width stacked TSVs with varying widths, where a first buried silicon via portion extends to the backside surface and a second portion with a smaller width extends to the active device layer, relaxing the aspect ratio limit and allowing for increased transistor density while minimizing mechanical stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional uniform-width TSVs are used, then manufacturing process is simple, but transistor density is limited due to large keep-out-regions
Solution Approach 1:
The TSV structure is segmented into multiple portions along its length, with each portion having a different width. The first portion has a larger width for mechanical stability and stress relief, while the second portion has a smaller width to reduce the keep-out-region and increase transistor density. This segmentation allows the TSV to satisfy both mechanical requirements and space constraints.
Solution Approach 2:
Different portions of the TSV structure are given different local qualities (widths) to optimize specific functions. The upper portion near the active device layer uses a smaller width to minimize interference with transistors, while the lower portion uses a larger width to provide mechanical support and reduce stress concentration.
2Area of stationary object
If TSV width is reduced to increase transistor density, then keep-out-region is minimized, but mechanical stress increases causing transistor functionality breakdown
Solution Approach 1:
The TSV is divided into portions with different widths to simultaneously minimize the keep-out-region and maintain mechanical reliability. The smaller-width portion reduces the keep-out-region for increased transistor density, while the larger-width portion provides mechanical support to prevent stress-induced transistor failure.
Solution Approach 2:
The width parameter of the TSV is changed along its length rather than maintaining a uniform width. This parameter variation allows optimization of both the keep-out-region size and mechanical stress distribution, with the width transitioning from larger at the base to smaller near the active device layer.
3Reliability
If copper-based TSVs are used, then electrical conductivity is improved, but thermal expansion mismatch with silicon increases mechanical stress
Solution Approach 1:
The width parameter of the copper-based TSV is varied along its length to compensate for thermal expansion mismatch. The larger-width portion at the base provides a buffer zone that accommodates differential thermal expansion between copper and silicon, while the smaller-width portion maintains good electrical conductivity with reduced stress concentration at the interface with the active device layer.
Data Source
AI summary
An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.