Stacked Micro Via PCB Manufacturing with Conductive Paste
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Solution Overview
Problem
The existing methods for manufacturing printed circuit boards face challenges such as stress-induced damage and unreliable interconnections due to adhesive shrinkage during curing, and the costly and time-consuming process of plating through-holes with copper material, which complicates quick assembly and alignment of interconnections.
Innovation Solution
A method involving the use of stacked micro vias with conductive paste fillings, eliminating the need for copper plating, and allowing for fabrication with one or two lamination cycles, using metal, ceramic, or FR4 substrates with protective films like Mylar, and forming micro vias through laser or mechanical drilling, to achieve stress-free and reliable interconnections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional through-hole drilling and copper plating processes are used, then reliable interconnection is achieved, but manufacturing time and cost increase significantly
Solution Approach 1:
The patent applies preliminary action by pre-forming vias and filling them with conductive material during the lamination process itself, rather than drilling and plating them afterward. The vias are created as part of the layer stacking process, and conductive paste is applied beforehand, eliminating the need for subsequent drilling and plating operations.
Solution Approach 2:
The patent merges multiple separate processes (lamination, via formation, and plating) into a single integrated lamination cycle. The circuit layers, vias, and conductive fillings are all processed together in one manufacturing step, significantly reducing the total number of process steps and manufacturing time.
2Strength
If adhesive curing process is used to bond circuit layers, then permanent physical bonding is achieved, but adhesive shrinkage causes stress and damage to the structure
Solution Approach 1:
The patent changes the material parameter by replacing traditional shrink-prone adhesives with low-shrinkage or shrink-compensating materials. This parameter change maintains the bonding strength while significantly reducing the adverse shrinkage effects that cause internal stress and structural damage during curing.
Solution Approach 2:
The patent applies beforehand cushioning by using materials and processes that pre-compensate for shrinkage effects. The low-shrinkage adhesive formulation and controlled curing process are designed in advance to minimize stress development, cushioning against the potential damage before it occurs.
3Adaptability or versatility
If multiple lamination cycles are used to achieve higher layer counts, then circuit complexity increases, but manufacturing complexity and error risk increase
Solution Approach 1:
The patent merges multiple lamination operations into a single comprehensive lamination cycle. All circuit layers are stacked and bonded simultaneously in one process, eliminating the need for multiple sequential lamination cycles and the associated alignment and bonding steps between separate cycles.
Solution Approach 2:
The patent applies preliminary action by pre-assembling all circuit layers with their respective vias and conductive elements before the final lamination. This pre-assembly preparation allows all layers to be bonded in a single cycle, reducing manufacturing complexity and error risk associated with multiple cycles.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces assembly costs and time, enhances registration accuracy, and allows for higher layer counts with fewer process steps, minimizing errors and increasing product quality and capacity, while eliminating the need for sequential lamination and plating processes.
Implementation Method 1
curing the lamination adhesive on the substrate of each the plurality of one-metal layer carriers to laminate the plurality of one-metal layer carriers with each other
Implementation Method 2
forming micro vias through laser or mechanical drilling
Implementation Method 3
forming micro vias through laser or mechanical drilling
Implementation Method 4
stacked micro vias with conductive paste fillings
Data Source
Figure 1a~1g
Figure 1h~1i
Figure 2
AI summary
A method of manufacturing at least a portion of a printed circuit board. The method includes: applying a lamination adhesive on a first plural-layer substrate that includes a plurality of circuit layers with at least one first metal pad on a first side of the first plural-layer substrate; applying a protective film on the lamination adhesive; forming at least one via into the lamination adhesive to expose the at least one metal pad on the first side of the first plural-layer substrate; filling at least one conductive paste into the at least one via formed in the lamination adhesive; removing the protective film to expose the lamination adhesive on the first plural-layer substrate; and attaching the first plural-layer substrate with a second plural-layer substrate that includes a plurality of circuit layers with at least one second metal pad on a second side of the second plural-layer substrate.