Stacked Microelectronic Assembly with Central Contacts and Thermal Management
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Solution Overview
Problem
Conventional multi-chip packages occupy more area on a circuit panel than the total surface area of individual chips due to chips being mounted side-by-side or stacked with contacts located centrally, limiting the compactness and height reduction of microelectronic assemblies.
Innovation Solution
A stacked microelectronic assembly design featuring a dielectric element with apertures and conductive elements, where first and second microelectronic elements are stacked with exposed contacts and connected via wire bonds through the apertures, and a heat spreader for thermal management, allowing for a compact and low-profile arrangement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If chips are mounted side-by-side on a single package substrate, then multiple chips can be accommodated in a single package, but the aggregate area occupied on the circuit panel is still greater than the total surface area of the individual chips
Solution Approach 1:
The patent transitions from a two-dimensional side-by-side chip arrangement to a three-dimensional stacked configuration. Multiple chips are arranged vertically one on top of another, utilizing the height dimension to reduce the planar footprint on the circuit panel. This dimensional change allows the aggregate area to approach the total surface area of the chips themselves.
Solution Approach 2:
The patent implements a nested structure where multiple chips are stacked vertically within a compact package housing. Each chip is positioned within the vertical space occupied by the package, similar to nested dolls, maximizing space utilization and minimizing the external footprint on the circuit panel.
2Area of stationary object
If chips are stacked one on top of another, then the area occupied on the circuit panel is reduced, but the overall height or dimension perpendicular to the circuit panel increases
Solution Approach 1:
The patent employs thin-film wiring layers and flexible interconnect structures that can be deposited on planar substrates. These thin films enable electrical connections between stacked chips without requiring thick rigid interconnectors, thereby minimizing the vertical height increase while maintaining the stacked configuration.
Solution Approach 2:
The patent replaces traditional mechanical wire bonds or thick trace interconnects with thin-film conductive layers deposited through semiconductor fabrication processes. This substitution reduces the vertical thickness required for interconnections between stacked chips, mitigating the height increase problem.
3Adaptability or versatility
If contacts are located in central regions of chips, then certain memory chip designs are enabled, but conventional packaging and interconnection methods become more difficult
Solution Approach 1:
The patent utilizes vertical stacking to bring centrally-located contacts of different chips into alignment through the height dimension. Wire bonds or conductive elements extend vertically through the stack to connect corresponding central contacts, transforming a difficult planar connection problem into a manageable vertical connection task.
Solution Approach 2:
The patent introduces intermediate conductive structures, such as vias or vertical interconnectors within the package substrate, that facilitate connections between the central contacts of stacked chips. These intermediaries simplify the manufacturing process by providing predefined connection paths through the package structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables a more compact and reduced-height microelectronic assembly that can be placed closer to neighboring structures, efficiently connecting multiple chips in a smaller area while effectively managing heat dissipation.
Implementation Method 1
a heat spreader thermally coupled to at least one of the first microelectronic element or the second microelectronic element
Data Source
AI summary
A microelectronic assembly includes a dielectric element that has oppositely-facing first and second surfaces and first and second apertures extending between the surfaces. The dielectric element further includes conductive elements. First and second microelectronic elements are stacked one on top of the another. The second microelectronic element has a plurality of contacts at a surface, which is spaced from the first surface of the dielectric element. Leads extend from contacts of the first and second microelectronic elements through respective apertures to at least some of the conductive elements. A heat spreader is thermally coupled to at least one of the first microelectronic element or the second microelectronic element.