Stacked Microelectronic Assembly with Through-Substrate Conductors
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Solution Overview
Problem
Conventional microelectronic assemblies occupy more area on circuit panels than necessary, especially when multiple chips are mounted side-by-side or stacked, due to the large size of chip packages and limited reduction in aggregate area, particularly for chips with contacts in central regions.
Innovation Solution
A stacked microelectronic assembly design featuring a substrate with oppositely-facing surfaces and apertures, where first and second microelectronic elements are stacked with leads connecting their contacts to substrate contacts, allowing for a more compact arrangement by exposing contacts beyond the edges of the first element and utilizing a dielectric element with conductive traces and wire bonds for efficient signal transmission and power regulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple chips are mounted side-by-side on a package substrate, then the chips can be interconnected, but the aggregate area occupied on the circuit panel remains greater than the total surface area of the individual chips
Solution Approach 1:
The patent transitions from a two-dimensional side-by-side chip arrangement to a three-dimensional stacked configuration. Multiple chips are vertically stacked on the package substrate, with upper chips positioned above lower chips. This vertical stacking enables chip interconnection while significantly reducing the horizontal footprint and aggregate area occupied on the circuit panel, directly resolving the technical contradiction between interconnection capability and area occupation.
2Area of stationary object
If chips are stacked one on top of another, then the area occupied on the circuit panel is reduced, but contacts in central regions of chips cannot be effectively connected
Solution Approach 1:
The patent introduces an intermediary substrate structure with through-substrate conductors that penetrate the package substrate vertically. These conductors serve as mediators to establish electrical connections between contacts on upper chips and lower chips in the stacked configuration. The intermediary substrate and its through-substrate conductors enable effective connection of centrally-located contacts despite the vertical stacking arrangement, resolving the contradiction between area reduction and connection efficiency.
3Ease of manufacture
If conventional chip packages are used, then individual chips can be mounted, but the package occupies considerably more area on the circuit panel than the chip itself
Solution Approach 1:
The patent merges multiple individual chip packages into a single integrated stacked package structure. Multiple chips are mounted on a common package substrate in a vertical stack, with their respective contacts interconnected through the substrate. This merging approach maintains the manufacturing ease of individual chip mounting while dramatically reducing the total package area occupied on the circuit panel, as the stacked configuration utilizes vertical space rather than horizontal expansion.
Data Source
AI summary
A microelectronic assembly can include a substrate having an aperture extending between first and second surfaces thereof, the substrate having substrate contacts at the first surface and terminals at the second surface. The microelectronic assembly can include a first microelectronic element having a front surface facing the first surface, a second microelectronic element having a front surface facing the first microelectronic element, and leads electrically connecting the contacts of the second microelectronic element with the terminals. The second microelectronic element can have contacts exposed at the front surface thereof beyond an edge of the first microelectronic element. The first microelectronic element can be configured to regenerate at least some signals received by the microelectronic assembly at the terminals and to transmit said signals to the second microelectronic element. The second microelectronic element can embody a greater number of active devices to provide memory storage array function than any other function.