Stacked Microelectronic Assemblies with Central Contacts
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Solution Overview
Problem
Conventional microelectronic assemblies with chips having contacts in central regions face challenges in minimizing the planar area occupied on circuit panels, especially when stacking multiple chips, as existing stacked arrangements do not efficiently reduce the aggregate area usage.
Innovation Solution
A microelectronic assembly design featuring a dielectric element with apertures and electrically conductive elements, along with first and second microelectronic elements, where leads extend from the elements' contacts to the dielectric's terminals, enabling efficient interconnection and signal transmission between the elements, allowing for compact stacking and reduced area occupation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If chips are stacked one on top of another in conventional arrangements, then the planar area occupied on circuit panels is reduced, but the aggregate area usage is still greater than the total surface area of the individual chips
Solution Approach 1:
The patent transitions from conventional side-by-side or simple vertical stacking to a multi-dimensional stacked arrangement where chips are positioned at different heights and orientations. The support structure enables chips to be stacked in multiple layers with varying positions, effectively utilizing three-dimensional space rather than just vertical stacking, thereby achieving superior area reduction while maintaining accessibility for connection.
Solution Approach 2:
The patent implements a nested stacking configuration where smaller chips or components are positioned within the footprint of larger chips in adjacent layers. The support structure allows inner chips to be nested within the bounding box of outer chips, creating a compact nested arrangement that maximizes space utilization and reduces the overall planar area occupied on the circuit panel.
2Area of stationary object
If chips with central contacts are stacked, then area is reduced, but efficient interconnection and signal transmission become more difficult
Solution Approach 1:
The patent introduces a support structure as an intermediary component between stacked chips with central contacts. This support structure provides dedicated connection points and conductive pathways that facilitate efficient electrical interconnection between chips. The intermediary structure bridges the gap between central contacts of adjacent chips, enabling straightforward signal and power transmission without requiring complex routing through the chip edges or backside.
Solution Approach 2:
The patent segments the interconnection function by separating the mechanical support function from the electrical connection function. The support structure is divided into distinct regions: mechanical support areas and electrical connection areas with conductive elements. This segmentation allows central contacts on chips to be efficiently connected to corresponding terminals on the support structure without compromising mechanical stability or electrical performance.
3Area of moving object
If conventional packaging is used, then chip area is preserved, but the overall height or dimension perpendicular to the circuit panel increases
Solution Approach 1:
The patent employs three-dimensional stacking arrangements that utilize vertical space more efficiently than conventional packaging. By positioning multiple chips at different heights and orientations on the support structure, the design achieves compact overall height while preserving the full area of each chip for functional use. The multi-layer configuration allows chips to be arranged in a space-efficient manner that minimizes the perpendicular dimension.
4Ease of operation
If more leads and conductive elements are added for interconnection, then signal transmission is facilitated, but inductance and noise increase
Solution Approach 1:
The patent optimizes the electrical parameters of the conductive elements by carefully controlling their geometry, material composition, and arrangement. The conductive elements are designed with appropriate cross-sectional areas, lengths, and configurations to minimize inductance and resistance. By adjusting these parameters, the support structure achieves low-inductance connections that facilitate high-speed signal transmission while minimizing noise and electromagnetic interference.
Solution Approach 2:
The support structure with its integrated conductive elements serves as an intermediary that provides optimized signal pathways between chips. The conductive elements are strategically positioned and dimensioned to create controlled impedance traces and minimize signal integrity issues. This intermediary structure enables efficient signal transmission while actively managing inductance and noise through its design, rather than using simple wire bonds or trace routing that would generate more interference.
Data Source
AI summary
A microelectronic assembly includes a dielectric element having first and second surfaces, first and second apertures extending between the first and second surfaces and defining a central region of the first surface between the first and second apertures, first and second microelectronic elements, and leads extending from contacts exposed at respective front surfaces of the first and second microelectronic elements to central terminals exposed at the central region. The front surface of the first microelectronic element can face the second surface of the dielectric element. The front surface of the second microelectronic element can face a rear surface of the first microelectronic element. The contacts of the second microelectronic element can project beyond an edge of the first microelectronic element. At least first and second ones of the leads can electrically interconnect a first central terminal of the central terminals with each of the first and second microelectronic elements.