Stacked Microelectronic Assembly with Central Contacts and Metallized Vias
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Solution Overview
Problem
Conventional microelectronic assemblies with central contacts, such as memory chips, face challenges in achieving compactness and reduced area occupation on circuit panels, as existing stacked chip arrangements do not effectively minimize the aggregate area occupied by multiple chips.
Innovation Solution
A stacked microelectronic assembly design featuring a first and second microelectronic element with exposed contacts, a dielectric region, metallized vias, and leads extending from the vias to terminals, allowing for efficient electrical connection and a compact footprint, with an overmold and support members to enhance structural integrity and connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional multi-chip module arrangements are used where chips are mounted side-by-side on a single package substrate, then the chips can be interconnected and mounted to a circuit panel, but the aggregate area occupied on the circuit panel is greater than the total surface area of the individual chips
Solution Approach 1:
The patent transitions from a two-dimensional side-by-side chip arrangement to a three-dimensional stacked arrangement. Multiple chips are vertically stacked one on top of another, with interconnection structures (such as conductive pillars, vias, and bonding wires) enabling electrical connections between chips in different layers. This vertical stacking dramatically reduces the aggregate footprint on the circuit panel while maintaining full interconnectivity among all chips in the module.
2Area of stationary object
If chips are stacked one on top of another in a vertical arrangement, then the aggregate area on the circuit panel is reduced, but effective electrical interconnection between stacked chips becomes more complex
Solution Approach 1:
The patent introduces intermediary connection structures that facilitate electrical interconnection between stacked chips. These intermediaries include conductive pillars extending from chip contacts through dielectric layers, metallized vias in substrate layers, and bonding wires or bumps that bridge adjacent chips. These intermediary elements simplify the direct connection problem by providing dedicated conductive pathways through the vertical stack, making the interconnection process more manageable despite the three-dimensional arrangement.
3Adaptability or versatility
If chip contacts are located in central regions of the chips, then certain semiconductor functions are achieved, but conventional stacked arrangements cannot effectively minimize the aggregate area occupied
Solution Approach 1:
The patent applies local quality by adapting the interconnection structure to the specific contact configuration of the chips. When chips have central contacts rather than edge contacts, the design incorporates central vias, conductive pillars, and bonding structures that originate from the chip centers. This localized adaptation ensures that the vertical stacking approach remains effective regardless of where the contacts are positioned on the chip surface, allowing central-contact chips to be stacked with the same area-reduction benefits as edge-contact chips.
Data Source
AI summary
The microelectronic assembly includes a first microelectronic element having a front surface, a plurality of contacts exposed at the front surface, and a rear surface remote from the front surface; a second microelectronic element having a front surface facing the rear surface of the first microelectronic element and projecting beyond an edge of the first microelectronic element, the second microelectronic element having a plurality of contacts exposed at its front surface; a dielectric region overlying the front surfaces of the microelectronic elements, the dielectric region having a major surface facing away from the microelectronic elements; metallized vias within openings in the dielectric region extending from the plurality of contacts of the first and second microelectronic elements; and leads extending along a major surface of the dielectric region from the vias to terminals exposed at the major surface.