Stacked Microelectronic Assembly with Interleaved Leads
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Solution Overview
Problem
Conventional stacked microelectronic packages face challenges related to complexity, cost, thickness, and testability, necessitating improved wafer-scale packaging processes.
Innovation Solution
A method involving the stacking and joining of microelectronic substrates with different orientations, where traces are exposed and leads are formed to be electrically isolated, allowing for the creation of stacked assemblies with interleaved leads and efficient electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If multiple microelectronic chips are stacked within a package to save space, then the package occupies less surface area on the substrate, but the package complexity increases
Solution Approach 1:
The package is divided into multiple discrete chip layers stacked vertically, with each layer containing microelectronic chips and interconnect structures. This segmentation allows the package to occupy less substrate area while managing complexity through modular layering and standardized interconnection interfaces between layers.
2Area of stationary object
If conventional stacked packaging methods are used, then space is saved, but the package thickness increases
Solution Approach 1:
The invention extracts and eliminates redundant interconnect structures and packaging materials from conventional stacked designs. By using direct chip-to-chip bonding with minimal intermediate layers and removing unnecessary packaging components, the package thickness is reduced while maintaining the space-saving vertical stacking architecture.
3Area of stationary object
If conventional stacked packages are used, then space efficiency is improved, but testability deteriorates
Solution Approach 1:
Test structures and measurement interfaces are incorporated into the package design during the manufacturing process rather than requiring post-packaging modifications. Test access points are pre-configured on external packaging elements, allowing for in-package testing and measurement without disassembling the stacked structure, thus maintaining space efficiency while improving testability.
4Area of stationary object
If conventional stacked packages are used, then space efficiency is improved, but reparability deteriorates
Solution Approach 1:
The package employs a nested modular structure where chips and interconnect layers are organized in replaceable units. This nesting allows for selective replacement of defective components or layers without requiring complete package disassembly, maintaining the compact vertical form factor while enabling targeted repairs and maintenance operations.
Data Source
AI summary
A method is provided for fabricating a stacked microelectronic assembly by steps including stacking and joining first and second like microelectronic substrates, each including a plurality of like microelectronic elements attached together at dicing lanes. Each microelectronic element has boundaries defined by edges including a first edge and a second edge. The first and second microelectronic substrates can be joined in different orientations, such that first edges of microelectronic elements of the first microelectronic substrate are aligned with second edges of microelectronic elements of the second microelectronic substrate. After exposing traces at the first and second edges of the microelectronic elements of the stacked microelectronic substrates, first and second leads can be formed which are connected to the exposed traces of the first and second microelectronic substrates, respectively. The second leads can be electrically isolated from the first leads.