Stacked Microelectronic Package with Monolithic Conductive Structure

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Solution Overview

Problem

Current microelectronic packaging technologies face challenges in efficiently stacking multiple chips to optimize space usage and establishing effective electrical connections between stacked chips and external components.

Innovation Solution

A microelectronic package design featuring vertically stacked microelectronic elements with a conductive structure that includes a continuous monolithic metal feature extending along the top surface and through an encapsulant to connect chip contacts to terminals, allowing for reduced-length conductive paths and efficient connection to external components.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If multiple chips are stacked vertically to save space, then area utilization is improved, but establishing reliable electrical connections between stacked chips and external components becomes more difficult

Engineering Contradiction:
Improvearea utilizationVSAvoidelectrical connection reliability
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent transitions from planar chip arrangements to vertical stacking, utilizing the third dimension (height) to arrange multiple chips. This dimensional change allows multiple chips to occupy a smaller footprint area while maintaining electrical connectivity through vertical conductive structures that extend through the encapsulant material.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The encapsulant material serves as an intermediary that simultaneously provides mechanical support and electrical insulation. Conductive structures embedded within the encapsulant act as mediators to establish electrical pathways between the stacked chips and external terminals, resolving the conflict between space savings and connection reliability.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If chips are stacked one on top of another, then space efficiency is improved, but the complexity of establishing electrical connections increases

Engineering Contradiction:
Improvespace efficiencyVSAvoidconnection structure complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent combines multiple functions into unified structures: the encapsulant simultaneously provides mechanical support, electrical insulation, and a medium for embedding conductive pathways. Conductive structures integrate multiple functions including electrical connection, structural support, and signal routing, thereby reducing overall system complexity despite vertical stacking.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The conductive structures serve multiple purposes: they provide electrical connectivity between stacked chips, extend connections to external terminals, and are embedded within the encapsulant for mechanical support. This multi-functionality reduces the need for separate dedicated components for each function.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If conductive structures extend through encapsulant to connect stacked chips, then electrical connectivity is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improveelectrical connectivityVSAvoidconductive structure alignment
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The conductive structures are pre-formed and positioned within the encapsulant material before final curing or assembly steps. This preliminary action allows for precise positioning to be established early in the manufacturing process, maintaining alignment accuracy throughout subsequent processing steps.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent utilizes changes in the physical state or properties of materials during manufacturing. The encapsulant material may be applied in a soft or uncured state to accommodate conductive structures, then cured or hardened to lock them in precise positions, thereby achieving high alignment accuracy without requiring extreme precision during all manufacturing steps.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS8786070B2Microelectronic package with stacked microelectronic elements and method for manufacture thereof
Publication Date: 2014.07.22 ADEIA SEMICONDUCTOR SOLUTIONS LLC
  • US8786070B2 patent drawing
  • US8786070B2 patent drawing
  • US8786070B2 patent drawing

AI summary

A microelectronic package may include a stacked microelectronic unit including at least first and second vertically stacked microelectronic elements each having a front face facing a top surface of the package. The front face of the first element may be adjacent the top surface, and the first element may overlie the front face of the second element such that at least a portion of the front face of the second element having an element contact thereon extends beyond an edge of the first element. A conductive structure may electrically connect a first terminal at the top surface to an element contact at the front face of the second element, and include a continuous monolithic metal feature extending along the top surface and through at least a portion of an encapsulant, which is between the top surface and the front face of the second element, towards the element contact.